linux-kernel - Re: [RFC PATCH 04/13] pci: pcsc: infer PCIe extended capabilities

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Message-ID: <20251009152415.00000b07@huawei.com>
Date: Thu, 9 Oct 2025 15:24:15 +0100
From: Jonathan Cameron <jonathan.cameron@...wei.com>
To: Evangelos Petrongonas <epetron@...zon.de>
CC: Bjorn Helgaas <bhelgaas@...gle.com>, Alex Williamson
	<alex.williamson@...hat.com>, "Rafael J . Wysocki" <rafael@...nel.org>, Len
 Brown <lenb@...nel.org>, Pasha Tatashin <pasha.tatashin@...een.com>, David
 Matlack <dmatlack@...gle.com>, Vipin Sharma <vipinsh@...gle.com>, Chris Li
	<chrisl@...nel.org>, Jason Miu <jasonmiu@...gle.com>, "Pratyush Yadav"
	<pratyush@...nel.org>, Stanislav Spassov <stanspas@...zon.de>,
	<linux-pci@...r.kernel.org>, <linux-acpi@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <nh-open-source@...zon.com>
Subject: Re: [RFC PATCH 04/13] pci: pcsc: infer PCIe extended capabilities

On Fri, 3 Oct 2025 09:00:40 +0000
Evangelos Petrongonas <epetron@...zon.de> wrote:

> Extend PCSC to support cacheability inference for PCIe extended
> capabilities located in the 4KB extended configuration space.
> 
> Similar to the capabilities, PCIe extended capabilities require
> traversal of the capability list to determine cacheability. The
> implementation identifies cacheable registers for capabilities used
> by the generic PCIe driver:
> 
> - Advanced Error Reporting (AER)
> - Access Control Services (ACS)
> - Alternative Routing-ID (ARI)
> - SR-IOV
> - Address Translation Services (ATS)
> - Page Request Interface (PRI)
> - Process Address Space ID (PASID)
> - Downstream Port Containment (DPC)
> - Precision Time Measurement (PTM)
> 
> The extended capability header (4 bytes) is always cached to enable
> efficient capability list traversal.
> 
> All the extended capabilities apart from the DPC are static. Regarding
> DPC, the DPC capabilities is read and based on its value the
> cacheability of RP* registers is inferred.
> 
> Signed-off-by: Evangelos Petrongonas <epetron@...zon.de>
> Signed-off-by: Stanislav Spassov <stanspas@...zon.de>
A few comments below.

> ---
>  drivers/pci/pcsc.c | 203 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 203 insertions(+)
> 
> diff --git a/drivers/pci/pcsc.c b/drivers/pci/pcsc.c
> index 29945eac4190..343f8b03831a 100644
> --- a/drivers/pci/pcsc.c
> +++ b/drivers/pci/pcsc.c

> +static void infer_extended_capabilities_pointers(struct pci_dev *dev)
> +{
> +	int pos = 0x100;
> +	u32 header;
> +	int cap_ver, cap_id;
> +	int i;
> +
	if (!IS_ENABLED(CONFIG_PCIE_PCSC))
		return;

is probably enough to allow the compiler to get rid of everything without
the ifdef magic.

> +	while (pos) {
> +		if (pos > 0xFFC || pos < 0x100)
> +			break;
> +
> +		pos &= ~0x3;
> +
> +		if (pcsc_hw_config_read(dev->bus, dev->devfn, pos, 4,
> +					&header) != PCIBIOS_SUCCESSFUL)
> +			break;
> +
> +		if (!header)
> +			break;
> +
> +		bitmap_set(dev->pcsc->cachable_bitmask, pos, 4);
> +		for (i = 0; i < 4; i++)
> +			pcsc_update_byte(dev, pos + i,
> +					 (header >> (i * 8)) & 0xFF);
> +
> +		cap_id = PCI_EXT_CAP_ID(header);
> +		cap_ver = PCI_EXT_CAP_VER(header);
> +
> +		pci_dbg(dev,
> +			"Extended capability ID %#x (ver %d) found at %#x, next cap at %#x\n",
> +			cap_id, cap_ver, pos, PCI_EXT_CAP_NEXT(header));
> +
> +		/* Check if this is a supported extended capability and infer cacheability */
> +		for (i = 0; i < ARRAY_SIZE(PCSCS_SUPPORTED_EXT_CAPABILITIES);
> +		     i++) {
> +			if (cap_id == PCSCS_SUPPORTED_EXT_CAPABILITIES[i]) {
> +				infer_extended_capability_cacheability(dev, pos,
> +								       cap_id);
> +				break;
> +			}
> +		}
> +
> +		pos = PCI_EXT_CAP_NEXT(header);
> +	}
> +}
> +#endif
> +
>  static void infer_cacheability(struct pci_dev *dev)
>  {
>  	if (WARN_ON(!dev || !dev->pcsc || !dev->pcsc->cfg_space))
> @@ -432,6 +631,10 @@ static void infer_cacheability(struct pci_dev *dev)
>  		}
>  
>  		infer_capabilities_pointers(dev);
> +#ifdef CONFIG_PCIE_PCSC
> +		if (pci_is_pcie(dev))
> +			infer_extended_capabilities_pointers(dev);
> +#endif
>  	}
>  }
>