linux-kernel - Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5

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Message-ID: <a75ndv2mzwy3niihi3o2ux7lrkue7h5avj2vcxgqhs3hasunfg@cosy2knsveey>
Date: Sat, 11 Oct 2025 18:57:56 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Abel Vesa <abel.vesa@...aro.org>
Cc: Qiang Yu <qiang.yu@....qualcomm.com>,
        Pankaj Patil <pankaj.patil@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
Subject: Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5

On Sat, Oct 11, 2025 at 02:43:14PM +0300, Abel Vesa wrote:
> On 25-10-10 00:08:31, Qiang Yu wrote:
> > On Wed, Oct 08, 2025 at 04:36:59PM +0300, Abel Vesa wrote:
> > > On 25-09-25 12:02:27, Pankaj Patil wrote:
> > > > From: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> > > > 
> > > > Describe PCIe5 controller and PHY. Also add required system resources like
> > > > regulators, clocks, interrupts and registers configuration for PCIe5.
> > > > 
> > > > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> > > > Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> > > > Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> > > > ---
> > > >  arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
> > > >  1 file changed, 207 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> > > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > @@ -951,7 +951,7 @@ gcc: clock-controller@...000 {
> > > >  				 <0>,
> > > >  				 <0>,
> > > >  				 <0>,
> > > > -				 <0>;
> > > > +				 <&pcie5_phy>;
> > > >  			#clock-cells = <1>;
> > > >  			#reset-cells = <1>;
> > > >  			#power-domain-cells = <1>;
> > > > @@ -2511,6 +2511,212 @@ pcie_west_slv_noc: interconnect@...0000 {
> > > >  			#interconnect-cells = <2>;
> > > >  		};
> > > >  
> > > > +		pcie5: pci@...0000 {
> > > > +			device_type = "pci";
> > > > +			compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> > > 
> > > The first compatible is definitely "qcom,pcie-glymur".
> > 
> > According to Documentation/devicetree/bindings/arm/qcom-soc.yaml
> > the preferred order is qcom,socname-ipblock.
> 
> Fair enough.
> 
> Now I wonder what happened when we added the one for x1e80100.

Our PCIe hosts mostly follow the legacy approach and nobody wanted to
change it up to now.

-- 
With best wishes
Dmitry