linux-kernel - RE: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node

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Message-ID:
 <TYCPR01MB11332C3B841AAD1EA8459129486ECA@TYCPR01MB11332.jpnprd01.prod.outlook.com>
Date: Sat, 11 Oct 2025 01:39:28 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Claudiu.Beznea <claudiu.beznea@...on.dev>, "lpieralisi@...nel.org"
	<lpieralisi@...nel.org>, "kwilczynski@...nel.org" <kwilczynski@...nel.org>,
	"mani@...nel.org" <mani@...nel.org>, "robh@...nel.org" <robh@...nel.org>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	"geert+renesas@...der.be" <geert+renesas@...der.be>, magnus.damm
	<magnus.damm@...il.com>, "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>
CC: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Claudiu Beznea
	<claudiu.beznea.uj@...renesas.com>, wsa+renesas
	<wsa+renesas@...g-engineering.com>
Subject: RE: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node



> -----Original Message-----
> From: Biju Das
> Sent: 10 October 2025 12:37
> To: 'Claudiu Beznea' <claudiu.beznea@...on.dev>; lpieralisi@...nel.org; kwilczynski@...nel.org;
> mani@...nel.org; robh@...nel.org; bhelgaas@...gle.com; krzk+dt@...nel.org; conor+dt@...nel.org;
> geert+renesas@...der.be; magnus.damm <magnus.damm@...il.com>; p.zabel@...gutronix.de
> Cc: linux-pci@...r.kernel.org; linux-renesas-soc@...r.kernel.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org; Claudiu Beznea <claudiu.beznea.uj@...renesas.com>; wsa+renesas <wsa+renesas@...g-
> engineering.com>
> Subject: RE: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node
> 
> Hi Claudiu,
> 
> > -----Original Message-----
> > From: Claudiu Beznea <claudiu.beznea@...on.dev>
> > Sent: 10 October 2025 12:18
> ,> Subject: Re: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node
> >
> > Hi, Biju,
> >
> > On 10/7/25 16:44, Biju Das wrote:
> > > Hi Claudiu,
> > >
> > >> -----Original Message-----
> > >> From: Claudiu <claudiu.beznea@...on.dev>
> > >> Sent: 07 October 2025 14:37
> > >> Subject: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe
> > >> node
> > >>
> > >> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> > >>
> > >> The RZ/G3S SoC has a variant (R9A08G045S33) which supports PCIe. Add the PCIe node.
> > >>
> > >> Tested-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
> > >> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> > >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> > >> ---
> > >>
> > >> Changes in v5:
> > >> - updated the last part of ranges and dma-ranges
> > >> - collected tags
> > >>
> > >> Changes in v4:
> > >> - moved the node to r9a08g045.dtsi
> > >> - dropped the "s33" from the compatible string
> > >> - added port node
> > >> - re-ordered properties to have them grouped together
> > >>
> > >> Changes in v3:
> > >> - collected tags
> > >> - changed the ranges flags
> > >>
> > >> Changes in v2:
> > >> - updated the dma-ranges to reflect the SoC capability; added a
> > >>   comment about it.
> > >> - updated clock-names, interrupt names
> > >> - dropped legacy-interrupt-controller node
> > >> - added interrupt-controller property
> > >> - moved renesas,sysc at the end of the node to comply with
> > >>   DT coding style
> > >>
> > >>  arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 66
> > >> ++++++++++++++++++++++
> > >>  1 file changed, 66 insertions(+)
> > >>
> > >> diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> > >> b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> > >> index 16e6ac614417..00b43377877e 100644
> > >> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> > >> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> > >> @@ -717,6 +717,72 @@ eth1: ethernet@...40000 {
> > >>  			status = "disabled";
> > >>  		};
> > >>
> > >> +		pcie: pcie@...40000 {
> > >> +			compatible = "renesas,r9a08g045-pcie";
> > >> +			reg = <0 0x11e40000 0 0x10000>;
> > >> +			ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
> > >> +			/* Map all possible DRAM ranges (4 GB). */
> > >> +			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1
> > >> +0x00000000>;
> > >
> > > On RZ/G3E, HW manual mentions PCIe can access up to a 36-bit address
> > > space (access to DDR and
> > PCIE0).
> > >
> > > Not sure about RZ/G3S?
> >
> > As of my knowledge/investigation, according to chapter 5.4.2.1 34-Bit
> > Address Space Access of HW manual, revision 1.10, on RZ/G3S there are
> > some bus masters that can access up to 34-bit address space, these
> > being SDHI/eMMC, GEthernet, USB2.0, DMAC. The rest can access up to 32-bit address space.
> 
> OK, Thanks for the info.
> 
> I am just wondering, later how to handle the Cross-Over 4G memory in driver as here we have size of
> 0x1_0000_0000 and start address is 0x4000_0000 which crosses the first 4G boundary.

I got confused with comparing RZ/G3E hardware manual. Looks like PCIe bus master does not
have any restriction.

Cheers,
Biju