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Message-ID: <20251012192330.6903-27-jernej.skrabec@gmail.com>
Date: Sun, 12 Oct 2025 21:23:26 +0200
From: Jernej Skrabec <jernej.skrabec@...il.com>
To: mripard@...nel.org,
wens@...e.org
Cc: maarten.lankhorst@...ux.intel.com,
tzimmermann@...e.de,
airlied@...il.com,
simona@...ll.ch,
samuel@...lland.org,
dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org,
Jernej Skrabec <jernej.skrabec@...il.com>
Subject: [PATCH 26/30] drm/sun4i: mixer: Add quirk for number of VI scalers
On DE2 and DE3, UI scalers are located right after VI scalers. So in
order to calculate proper UI scaler base address, number of VI scalers
must be known. In practice, it is same as number of VI channels, but it
doesn't need to be.
Let's make a quirk for this number. Code for configuring channels and
associated functions won't have access to vi_num quirk anymore after
rework for independent planes.
Signed-off-by: Jernej Skrabec <jernej.skrabec@...il.com>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 11 +++++++++++
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 10 +++++-----
3 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 78bbfbe62833..f9131396f22f 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -708,6 +708,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
.scaler_mask = 0xf,
.scanline_yuv = 2048,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 3,
.vi_num = 1,
};
@@ -718,6 +719,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
.scaler_mask = 0x3,
.scanline_yuv = 2048,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 1,
.vi_num = 1,
};
@@ -729,6 +731,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
.scaler_mask = 0xf,
.scanline_yuv = 2048,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 3,
.vi_num = 1,
};
@@ -740,6 +743,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
.scaler_mask = 0xf,
.scanline_yuv = 2048,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 3,
.vi_num = 1,
};
@@ -751,6 +755,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
.scaler_mask = 0x3,
.scanline_yuv = 2048,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 1,
.vi_num = 1,
};
@@ -761,6 +766,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.ui_num = 1,
.scaler_mask = 0x3,
.scanline_yuv = 2048,
+ .vi_scaler_num = 2,
.ccsc = CCSC_MIXER0_LAYOUT,
.mod_rate = 150000000,
};
@@ -772,6 +778,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
.scaler_mask = 0x3,
.scanline_yuv = 2048,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 1,
.vi_num = 1,
};
@@ -783,6 +790,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
.scaler_mask = 0x1,
.scanline_yuv = 1024,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 0,
.vi_num = 1,
};
@@ -794,6 +802,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
.scaler_mask = 0xf,
.scanline_yuv = 4096,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 3,
.vi_num = 1,
};
@@ -805,6 +814,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
.scaler_mask = 0x3,
.scanline_yuv = 2048,
.de2_fcc_alpha = 1,
+ .vi_scaler_num = 1,
.ui_num = 1,
.vi_num = 1,
};
@@ -814,6 +824,7 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
.mod_rate = 600000000,
.scaler_mask = 0xf,
.scanline_yuv = 4096,
+ .vi_scaler_num = 1,
.ui_num = 3,
.vi_num = 1,
};
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index def07afd37e1..40b800022237 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -178,6 +178,7 @@ enum sun8i_mixer_type {
* @scaline_yuv: size of a scanline for VI scaler for YUV formats.
* @de2_fcc_alpha: use FCC for missing DE2 VI alpha capability
* Most DE2 cores has FCC. If number of VI planes is one, enable this.
+ * @vi_scaler_num: Number of VI scalers. Used on DE2 and DE3.
* @map: channel map for DE variants processing YUV separately (DE33)
*/
struct sun8i_mixer_cfg {
@@ -189,6 +190,7 @@ struct sun8i_mixer_cfg {
unsigned int de_type;
unsigned int scanline_yuv;
unsigned int de2_fcc_alpha : 1;
+ unsigned int vi_scaler_num;
unsigned int map[6];
};
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
index c0947ccf675b..0ba1482688d7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
@@ -91,16 +91,16 @@ static const u32 lan2coefftab16[240] = {
static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
{
- int vi_num = mixer->cfg->vi_num;
+ int offset = mixer->cfg->vi_scaler_num;
if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
return DE3_VI_SCALER_UNIT_BASE +
- DE3_VI_SCALER_UNIT_SIZE * vi_num +
- DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);
+ DE3_VI_SCALER_UNIT_SIZE * offset +
+ DE3_UI_SCALER_UNIT_SIZE * (channel - offset);
else
return DE2_VI_SCALER_UNIT_BASE +
- DE2_VI_SCALER_UNIT_SIZE * vi_num +
- DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num);
+ DE2_VI_SCALER_UNIT_SIZE * offset +
+ DE2_UI_SCALER_UNIT_SIZE * (channel - offset);
}
static int sun8i_ui_scaler_coef_index(unsigned int step)
--
2.51.0
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