lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20251012023714.GF20642@nxa18884-linux.ap.freescale.net>
Date: Sun, 12 Oct 2025 10:37:14 +0800
From: Peng Fan <peng.fan@....nxp.com>
To: Jonas Rebmann <jre@...gutronix.de>
Cc: Andrew Lunn <andrew@...n.ch>, Vladimir Oltean <olteanv@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Liam Girdwood <lgirdwood@...il.com>,
	Mark Brown <broonie@...nel.org>,
	Shengjiu Wang <shengjiu.wang@....com>,
	Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Vladimir Oltean <vladimir.oltean@....com>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-sound@...r.kernel.org, imx@...ts.linux.dev,
	linux-arm-kernel@...ts.infradead.org,
	David Jander <david@...tonic.nl>,
	Lucas Stach <l.stach@...gutronix.de>,
	Oleksij Rempel <o.rempel@...gutronix.de>
Subject: Re: [PATCH v3 3/3] arm64: dts: add Protonic PRT8ML board

On Wed, Sep 24, 2025 at 10:34:14AM +0200, Jonas Rebmann wrote:
>Add devicetree for the Protonic PRT8ML.
>
>The board is similar to the Protonic PRT8MM but i.MX8MP based.
>
>Some features have been removed as the drivers haven't been mainlined
>yet or other issues where encountered:
> - Stepper motors to be controlled using motion control subsystem
> - MIPI/DSI to eDP USB alt-mode
> - Onboard T1 ethernet (10BASE-T1L+PoDL, 100BASE-T1+PoDL, 1000BASE-T1)
>
>Signed-off-by: David Jander <david@...tonic.nl>
>Signed-off-by: Lucas Stach <l.stach@...gutronix.de>
>Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
>Signed-off-by: Jonas Rebmann <jre@...gutronix.de>
>---
> arch/arm64/boot/dts/freescale/Makefile          |   1 +
> arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts | 501 ++++++++++++++++++++++++
> 2 files changed, 502 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
>index 525ef180481d..0c9abfa8d23d 100644
>--- a/arch/arm64/boot/dts/freescale/Makefile
>+++ b/arch/arm64/boot/dts/freescale/Makefile
>@@ -228,6 +228,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
> imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
>+dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts b/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts
>new file mode 100644
>index 000000000000..afca368ea1fd
>--- /dev/null
>+++ b/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts
>@@ -0,0 +1,501 @@
>+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>+/*
>+ * Copyright 2020 Protonic Holland
>+ * Copyright 2019 NXP
>+ */
>+
>+/dts-v1/;
>+
>+#include "imx8mp.dtsi"
>+
>+/ {
>+	model = "Protonic PRT8ML";
>+	compatible = "prt,prt8ml", "fsl,imx8mp";
>+
>+	chosen {
>+		stdout-path = &uart4;
>+	};
>+
>+	pcie_refclk: pcie0-refclk {
>+		compatible = "fixed-clock";
>+		#clock-cells = <0>;
>+		clock-frequency = <100000000>;
>+	};
>+
>+	pcie_refclk_oe: pcie0-refclk-oe {
>+		compatible = "gpio-gate-clock";
>+		pinctrl-names = "default";
>+		pinctrl-0 = <&pinctrl_pcie_refclk>;
>+		clocks = <&pcie_refclk>;
>+		#clock-cells = <0>;
>+		enable-gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
>+	};
>+};
>+
>+&A53_0 {
>+	cpu-supply = <&fan53555>;
>+};
>+
>+&A53_1 {
>+	cpu-supply = <&fan53555>;
>+};
>+
>+&A53_2 {
>+	cpu-supply = <&fan53555>;
>+};
>+
>+&A53_3 {
>+	cpu-supply = <&fan53555>;
>+};
>+
>+&a53_opp_table {
>+	opp-1200000000 {
>+		opp-microvolt = <900000>;
>+	};
>+
>+	opp-1600000000 {
>+		opp-microvolt = <980000>;
>+	};
>+
>+	/delete-node/ opp-1800000000;

Why drop this?

>+};
>+
>+&ecspi2 {
>+	pinctrl-names = "default";
>+	pinctrl-0 = <&pinctrl_ecspi2>;
>+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;

>+	/delete-property/ dmas;
>+	/delete-property/ dma-names;

Why remove dmas?


>+	status = "okay";
>+
>+
>+&iomuxc {
>+
>+	pinctrl_tps65987ddh_0: tps65987ddh_0grp {

tps65987ddh_0grp - > tps65987ddh-0grp

>+		fsl,pins = <
>+			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x1d0
>+		>;
>+	};
>+
>+	pinctrl_tps65987ddh_1: tps65987ddh_1grp {

tps65987ddh_1grp -> tps65987ddh-1grp

>+		fsl,pins = <
>+			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15	0x1d0
>+		>;

Regards
Peng

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ