linux-kernel - Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

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Message-Id: <031395FE-C51C-45A7-85A3-CC4A25EB6066@gmail.com>
Date: Sun, 12 Oct 2025 18:00:36 +0800
From: "Han Gao (Revy)" <rabenda.cn@...il.com>
To: Anup Patel <apatel@...tanamicro.com>
Cc: "Han Gao (Revy)" <rabenda.cn@...il.com>,
 Sunil V L <sunilvl@...tanamicro.com>,
 "Rafael J . Wysocki" <rafael@...nel.org>,
 Palmer Dabbelt <palmer@...belt.com>,
 Paul Walmsley <paul.walmsley@...ive.com>,
 Alexandre Ghiti <alex@...ti.fr>,
 Atish Patra <atish.patra@...ux.dev>,
 Andrew Jones <ajones@...tanamicro.com>,
 Anup Patel <anup@...infault.org>,
 linux-riscv@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent
 devices

> On Aug 20, 2025, at 23:23, Anup Patel <apatel@...tanamicro.com> wrote:
> 
> The pgprot_dmacoherent() is used when allocating memory for
> non-coherent devices and by default pgprot_dmacoherent() is
> same as pgprot_noncached() unless architecture overrides it.
> 
> Currently, there is no pgprot_dmacoherent() definition for
> RISC-V hence non-coherent device memory is being mapped as
> IO thereby making CPU access to such memory slow.
> 
> Define pgprot_dmacoherent() to be same as pgprot_writecombine()
> for RISC-V so that CPU access non-coherent device memory as
> NOCACHE which is better than accessing it as IO.
> 
> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
Tested-by: Han Gao <rabenda.cn@...il.com>
> ---
> arch/riscv/include/asm/pgtable.h | 2 ++
> 1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 91697fbf1f90..00d8bdaf1e8d 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -653,6 +653,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> return __pgprot(prot);
> }
> 
> +#define pgprot_dmacoherent pgprot_writecombine
> +
> /*
>  * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
>  * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> -- 
> 2.43.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 

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