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Message-ID: <20251013153526.2276556-4-elder@riscstar.com>
Date: Mon, 13 Oct 2025 10:35:20 -0500
From: Alex Elder <elder@...cstar.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
bhelgaas@...gle.com,
lpieralisi@...nel.org,
kwilczynski@...nel.org,
mani@...nel.org,
vkoul@...nel.org,
kishon@...nel.org
Cc: dlan@...too.org,
guodong@...cstar.com,
pjw@...nel.org,
palmer@...belt.com,
aou@...s.berkeley.edu,
alex@...ti.fr,
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christian.bruel@...s.st.com,
shradha.t@...sung.com,
krishna.chundru@....qualcomm.com,
qiang.yu@....qualcomm.com,
namcao@...utronix.de,
thippeswamy.havalige@....com,
inochiama@...il.com,
devicetree@...r.kernel.org,
linux-pci@...r.kernel.org,
linux-phy@...ts.infradead.org,
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linux-kernel@...r.kernel.org
Subject: [PATCH v2 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller
Add the Device Tree binding for the PCIe root complex found on the
SpacemiT K1 SoC. This device is derived from the Synopsys Designware
PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2
link speeds (5 GT/sec). One of the ports uses a combo PHY, which is
typically used to support a USB 3 port.
Signed-off-by: Alex Elder <elder@...cstar.com>
---
v2: - Renamed the binding, using "host controller"
- Added '>' to the description, and reworded it a bit
- Added reference to /schemas/pci/snps,dw-pcie.yaml
- Fixed and renamed the compatible string
- Renamed the PMU property, and fixed its description
- Consistently omit the period at the end of descriptions
- Renamed the "global" clock to be "phy"
- Use interrupts rather than interrupts-extended, and name the
one interrupt "msi" to make clear its purpose
- Added a vpcie3v3-supply property
- Dropped the max-link-speed property
- Changed additionalProperties to unevaluatedProperties
- Dropped the label and status property from the example
.../bindings/pci/spacemit,k1-pcie-host.yaml | 156 ++++++++++++++++++
1 file changed, 156 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
new file mode 100644
index 0000000000000..87745d49c53a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCI Express Host Controller
+
+maintainers:
+ - Alex Elder <elder@...cstar.com>
+
+description: >
+ The SpacemiT K1 SoC PCIe host controller is based on the Synopsys
+ DesignWare PCIe IP. The controller uses the DesignWare built-in
+ MSI interrupt controller, and supports 256 MSIs.
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: spacemit,k1-pcie
+
+ reg:
+ items:
+ - description: DesignWare PCIe registers
+ - description: ATU address space
+ - description: PCIe configuration space
+ - description: Link control registers
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: atu
+ - const: config
+ - const: link
+
+ spacemit,apmu:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ A phandle that refers to the APMU system controller, whose
+ regmap is used in managing resets and link state, along with
+ and offset of its reset control register.
+ items:
+ - items:
+ - description: phandle to APMU system controller
+ - description: register offset
+
+ clocks:
+ items:
+ - description: DWC PCIe Data Bus Interface (DBI) clock
+ - description: DWC PCIe application AXI-bus master interface clock
+ - description: DWC PCIe application AXI-bus slave interface clock
+
+ clock-names:
+ items:
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ resets:
+ items:
+ - description: DWC PCIe Data Bus Interface (DBI) reset
+ - description: DWC PCIe application AXI-bus master interface reset
+ - description: DWC PCIe application AXI-bus slave interface reset
+ - description: Global reset; must be deasserted for PHY to function
+
+ reset-names:
+ items:
+ - const: dbi
+ - const: mstr
+ - const: slv
+ - const: phy
+
+ interrupts:
+ items:
+ - description: Interrupt used for MSIs
+
+ interrupt-names:
+ const: msi
+
+ phys:
+ maxItems: 1
+
+ vpcie3v3-supply:
+ description:
+ A phandle for 3.3v regulator to use for PCIe
+
+ device_type:
+ const: pci
+
+ num-viewport:
+ const: 8
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - spacemit,apmu
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - interrupts
+ - interrupt-names
+ - phys
+ - vpcie3v3-supply
+ - device_type
+ - num-viewport
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k1-syscon.h>
+ pcie@...00000 {
+ compatible = "spacemit,k1-pcie";
+ reg = <0xca400000 0x00001000>,
+ <0xca700000 0x0001ff24>,
+ <0x9f000000 0x00002000>,
+ <0xc0c20000 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x9f002000 0x0 0x00100000>,
+ <0x02000000 0x0 0x90000000 0x90000000 0x0 0x0f000000>;
+ interrupts = <142>;
+ interrupt-names = "msi";
+ clocks = <&syscon_apmu CLK_PCIE1_DBI>,
+ <&syscon_apmu CLK_PCIE1_MASTER>,
+ <&syscon_apmu CLK_PCIE1_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE1_DBI>,
+ <&syscon_apmu RESET_PCIE1_MASTER>,
+ <&syscon_apmu RESET_PCIE1_SLAVE>,
+ <&syscon_apmu RESET_PCIE1_GLOBAL>;
+ reset-names = "dbi",
+ "mstr",
+ "slv",
+ "phy";
+ phys = <&pcie1_phy>;
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ device_type = "pci";
+ num-viewport = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ spacemit,apmu = <&syscon_apmu 0x3d4>;
+ };
--
2.48.1
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