Message-ID: <20251013210318.3879203-1-cmirabil@redhat.com>
Date: Mon, 13 Oct 2025 17:03:18 -0400
From: Charles Mirabile <cmirabil@...hat.com>
To: samuel.holland@...ive.com
Cc: alex@...ti.fr,
	aou@...s.berkeley.edu,
	cmirabil@...hat.com,
	dramforever@...e.com,
	linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	lzampier@...hat.com,
	palmer@...belt.com,
	paul.walmsley@...ive.com,
	tglx@...utronix.de,
	zhangxincheng@...rarisc.com
Subject: Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC

Hi Samuel - 

On Mon, Oct 13, 2025 at 02:00:29PM -0500, Samuel Holland wrote:
> Hi Lucas,
> 
> On 2025-10-13 6:15 AM, Lucas Zampieri wrote:
> > From: Charles Mirabile <cmirabil@...hat.com>
> > 
> > Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to
> > work around a known hardware bug with IRQ claiming.
> > 
> > When claiming an interrupt on the DP1000 PLIC all other interrupts must be
> > disabled before the claim register is accessed to prevent incorrect
> > handling of the interrupt.
> > 
> > When the PLIC_QUIRK_CLAIM_REGISTER is present, during plic_handle_irq
> > the enable state of all interrupts is saved and then all interrupts
> > except for the first pending one are disabled before reading the claim
> > register. The interrupts are then restored before further processing of
> > the claimed interrupt continues.
> 
> Since the workaround requires scanning the pending bits for each interrupt
> anyway, it would be simpler and more efficient to ignore the claim register
> entirely. Call generic_handle_domain_irq() for each interrupt that is (enabled
> AND pending), then clear the pending bit. Then you would not need to save and
> restore the enable registers.
> 
> > The driver matches on "ultrarisc,cp100-plic" to apply the quirk to all
> > SoCs using UR-CP100 cores, regardless of the specific SoC implementation.
> > This has no impact on other platforms.
> > 
> > Co-developed-by: Zhang Xincheng <zhangxincheng@...rarisc.com>
> > Signed-off-by: Zhang Xincheng <zhangxincheng@...rarisc.com>
> > Signed-off-by: Charles Mirabile <cmirabil@...hat.com>
> > Signed-off-by: Lucas Zampieri <lzampier@...hat.com>
> > ---
> >  drivers/irqchip/irq-sifive-plic.c | 83 ++++++++++++++++++++++++++++++-
> >  1 file changed, 82 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index 9c4af7d58846..a7b51a925e96 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -49,6 +49,8 @@
> >  #define CONTEXT_ENABLE_BASE		0x2000
> >  #define     CONTEXT_ENABLE_SIZE		0x80
> > 
> > +#define PENDING_BASE                    0x1000
> > +
> >  /*
> >   * Each hart context has a set of control registers associated with it.  Right
> >   * now there's only two: a source priority threshold over which the hart will
> > @@ -63,6 +65,7 @@
> >  #define	PLIC_ENABLE_THRESHOLD		0
> > 
> >  #define PLIC_QUIRK_EDGE_INTERRUPT	0
> > +#define PLIC_QUIRK_CLAIM_REGISTER	1
> > 
> >  struct plic_priv {
> >  	struct fwnode_handle *fwnode;
> > @@ -367,6 +370,82 @@ static const struct irq_domain_ops plic_irqdomain_ops = {
> >  	.free		= irq_domain_free_irqs_top,
> >  };
> > 
> > +static bool dp1000_isolate_pending_irq(int nr_irq_groups, u32 ie[],
> > +				       void __iomem *pending,
> > +				       void __iomem *enable)
> > +{
> > +	u32 pending_irqs = 0;
> > +	int i, j;
> > +
> > +	/* Look for first pending interrupt */
> > +	for (i = 0; i < nr_irq_groups; i++) {
> > +		pending_irqs = ie[i] & readl(pending + i * sizeof(u32));
> > +		if (pending_irqs)
> > +			break;
> > +	}
> > +
> > +	if (!pending_irqs)
> > +		return false;
> > +
> > +	/* Disable all interrupts but the first pending one */
> > +	for (j = 0; j < nr_irq_groups; j++) {
> > +		u32 new_mask = 0;
> > +
> > +		if (j == i)
> > +			/* Extract mask with lowest set bit */
> > +			new_mask = (pending_irqs & -pending_irqs);
> > +
> > +		writel(new_mask, enable + j * sizeof(u32));
> > +	}
> > +
> > +	return true;
> > +}
> > +
> > +static irq_hw_number_t dp1000_get_hwirq(struct plic_handler *handler,
> > +					void __iomem *claim)
> > +{
> > +	void __iomem *enable = handler->enable_base;
> > +	void __iomem *pending = handler->priv->regs + PENDING_BASE;
> > +	int nr_irqs = handler->priv->nr_irqs;
> > +	int nr_irq_groups = DIV_ROUND_UP(nr_irqs, 32);
> > +	int i;
> > +	u32 ie[32] = { 0 };
> > +	irq_hw_number_t hwirq = 0;
> > +
> > +	raw_spin_lock(&handler->enable_lock);
> > +
> > +	/* Save current interrupt enable state */
> > +	for (i = 0; i < nr_irq_groups; i++)
> > +		ie[i] = readl(enable + i * sizeof(u32));
> > +
> > +	if (!dp1000_isolate_pending_irq(nr_irq_groups, ie, pending, enable))
> > +		goto out;
> > +
> > +	hwirq = readl(claim);
> > +
> > +	/* Restore previous state */
> > +	for (i = 0; i < nr_irq_groups; i++)
> > +		writel(ie[i], enable + i * sizeof(u32));
> > +out:
> > +	raw_spin_unlock(&handler->enable_lock);
> > +	return hwirq;
> > +}
> > +
> > +static irq_hw_number_t plic_get_hwirq(struct plic_handler *handler,
> > +				      void __iomem *claim)
> > +{
> > +	/*
> > +	 * Due to a hardware bug in the implementation of the claim register
> > +	 * in the UltraRISC DP1000 platform, other interrupts must be disabled
> > +	 * before reading the claim register and restored afterwards.
> > +	 */
> > +
> > +	if (test_bit(PLIC_QUIRK_CLAIM_REGISTER, &handler->priv->plic_quirks))
> > +		return dp1000_get_hwirq(handler, claim);
> > +
> > +	return readl(claim);
> > +}
> > +
> >  /*
> >   * Handling an interrupt is a two-step process: first you claim the interrupt
> >   * by reading the claim register, then you complete the interrupt by writing
> > @@ -384,7 +463,7 @@ static void plic_handle_irq(struct irq_desc *desc)
> > 
> >  	chained_irq_enter(chip, desc);
> > 
> > -	while ((hwirq = readl(claim))) {
> > +	while ((hwirq = plic_get_hwirq(handler, claim))) {
> 
> This is the hot path for interrupt handling. Instead of checking for the quirk
> on every interrupt, please create a new function that you conditionally pass to
> irq_set_chained_handler(), so the quirk check only happens once at boot.
> 
> Regards,
> Samuel
> 
> >  		int err = generic_handle_domain_irq(handler->priv->irqdomain,
> >  						    hwirq);
> >  		if (unlikely(err)) {
> > @@ -432,6 +511,8 @@ static const struct of_device_id plic_match[] = {
> >  	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
> >  	{ .compatible = "thead,c900-plic",
> >  	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
> > +	{ .compatible = "ultrarisc,cp100-plic",
> > +	  .data = (const void *)BIT(PLIC_QUIRK_CLAIM_REGISTER) },
> >  	{}
> >  };
> > 
> > --
> > 2.51.0
> > 
> 

Is something like this closer to what you had in mind? I tried it on the
dp1000 and it doesn't work. Obviously it is concievable that I messed up
the logic here, but it also might be the case that reading the claim
register is integral to the proper functioning of the pending bits.

I can confirm that a more minimal change that just moves the quirk check
out of the hot path is fine. Would that be acceptable even if it is not
the most efficient? (in essense take the hunk with new functions from
the original patch but revert the change to `plic_handle_irq` and then add
the hunk that changes probe from this proposed patch and then create
the `plic_handle_irq_dp1000` function as a copy of `plic_handle_irq` where
`dp1000_get_hwirq` is in the loop instead of `readl(claim)`).

Best - Charlie

---
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 9c4af7d58846..fcf520ed33fd 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -49,6 +49,8 @@
 #define CONTEXT_ENABLE_BASE		0x2000
 #define     CONTEXT_ENABLE_SIZE		0x80
 
+#define PENDING_BASE                    0x1000
+
 /*
  * Each hart context has a set of control registers associated with it.  Right
  * now there's only two: a source priority threshold over which the hart will
@@ -63,6 +65,7 @@
 #define	PLIC_ENABLE_THRESHOLD		0
 
 #define PLIC_QUIRK_EDGE_INTERRUPT	0
+#define PLIC_QUIRK_CLAIM_REGISTER	1
 
 struct plic_priv {
 	struct fwnode_handle *fwnode;
@@ -367,6 +370,53 @@ static const struct irq_domain_ops plic_irqdomain_ops = {
 	.free		= irq_domain_free_irqs_top,
 };
 
+static int dp1000_find_pending_irq(struct plic_handler *handler, void __iomem *pending)
+{
+	void __iomem *enable = handler->enable_base;
+	int nr_irqs = handler->priv->nr_irqs;
+	int nr_irq_groups = DIV_ROUND_UP(nr_irqs, 32);
+	u32 pending_irqs = 0;
+	int i;
+
+	raw_spin_lock(&handler->enable_lock);
+	for (i = 0; i < nr_irq_groups; i++) {
+		u32 enable_mask = readl(enable + i * sizeof(u32));
+		u32 pending_mask = readl(pending + i * sizeof(u32));
+		if ((pending_irqs = enable_mask & pending_mask))
+			break;
+	}
+	raw_spin_unlock(&handler->enable_lock);
+
+	if (!pending_irqs)
+		return 0;
+
+	return 32 * i + __ffs(pending_irqs);
+}
+
+static void plic_handle_irq_dp1000(struct irq_desc *desc)
+{
+	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
+	void __iomem *pending = handler->priv->regs + PENDING_BASE;
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	irq_hw_number_t hwirq;
+
+	WARN_ON_ONCE(!handler->present);
+
+	chained_irq_enter(chip, desc);
+
+	while ((hwirq = dp1000_find_pending_irq(handler, pending))) {
+		int err = generic_handle_domain_irq(handler->priv->irqdomain,
+						    hwirq);
+		__plic_toggle(pending, hwirq, 0);
+		if (unlikely(err)) {
+			pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n",
+					    handler->priv->fwnode, hwirq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
 /*
  * Handling an interrupt is a two-step process: first you claim the interrupt
  * by reading the claim register, then you complete the interrupt by writing
@@ -432,6 +482,8 @@ static const struct of_device_id plic_match[] = {
 	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
 	{ .compatible = "thead,c900-plic",
 	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
+	{ .compatible = "ultrarisc,dp1000-plic",
+	  .data = (const void *)BIT(PLIC_QUIRK_CLAIM_REGISTER) },
 	{}
 };
 
@@ -666,12 +718,16 @@ static int plic_probe(struct fwnode_handle *fwnode)
 		}
 
 		if (global_setup) {
+			void (*handler_fn)(struct irq_desc *) = plic_handle_irq;
+			if (test_bit(PLIC_QUIRK_CLAIM_REGISTER, &handler->priv->plic_quirks))
+				handler_fn = plic_handle_irq_dp1000;
+
 			/* Find parent domain and register chained handler */
 			domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
 			if (domain)
 				plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
 			if (plic_parent_irq)
-				irq_set_chained_handler(plic_parent_irq, plic_handle_irq);
+				irq_set_chained_handler(plic_parent_irq, handler_fn);
 
 			cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
 					  "irqchip/sifive/plic:starting",
-- 
2.43.0

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