linux-kernel - Re: [PATCH v2 4/9] arm64: dts: qcom: ipq5424: Add QPIC SPI NAND controller support

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Message-ID: <911ee444-25a9-a645-d14f-72fc239e5eb7@quicinc.com>
Date: Mon, 13 Oct 2025 11:40:22 +0530
From: Md Sadre Alam <quic_mdalam@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>, <broonie@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <andersson@...nel.org>, <konradybcio@...nel.org>, <vkoul@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-spi@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <dmaengine@...r.kernel.org>
CC: <quic_varada@...cinc.com>
Subject: Re: [PATCH v2 4/9] arm64: dts: qcom: ipq5424: Add QPIC SPI NAND
 controller support



On 10/8/2025 6:00 PM, Konrad Dybcio wrote:
> On 10/8/25 11:04 AM, Md Sadre Alam wrote:
>> Add device tree nodes for QPIC SPI NAND flash controller support
>> on IPQ5424 SoC.
>>
>> The IPQ5424 SoC includes a QPIC controller that supports SPI NAND flash
>> devices with hardware ECC capabilities and DMA support through BAM
>> (Bus Access Manager).
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
>> ---
> 
> [...]
> 
>> +		qpic_bam: dma-controller@...4000 {
>> +			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
>> +			reg = <0x0 0x07984000 0x0 0x1c000>;
>> +			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_QPIC_AHB_CLK>;
>> +			clock-names = "bam_clk";
>> +			#dma-cells = <1>;
>> +			qcom,ee = <0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		qpic_nand: spi@...0000 {
>> +			compatible = "qcom,ipq5424-snand", "qcom,ipq9574-snand";
>> +			reg = <0x0 0x079b0000 0x0 0x10000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			clocks = <&gcc GCC_QPIC_CLK>,
>> +				 <&gcc GCC_QPIC_AHB_CLK>,
>> +				 <&gcc GCC_QPIC_IO_MACRO_CLK>;
>> +			clock-names = "core", "aon", "iom";
> 
> 1 a line, please, also below
ok
> 
>> +			dmas = <&qpic_bam 0>,
>> +			       <&qpic_bam 1>,
>> +			       <&qpic_bam 2>;
>> +			dma-names = "tx", "rx", "cmd";
>> +			status = "disabled";
> 
> Is there anything preventing us from enabling both these nodes by
> default on all boards (maybe secure configuration or required
> regulators)?
We can't enable NAND by default in the common DTSI because the GPIOs are 
shared between eMMC and NAND.The decision to enable NAND must be made at 
the board-specific level, depending on the flash type used on that
particular board or RDP.Enabling it globally could lead to conflicts on 
platforms where eMMC is present.

Thanks,
Alam.