Message-ID: <CAPd4Wez7eLunDbCmKs19S=q-DM3-kUs0=wwjxRi+pq1waq1RqA@mail.gmail.com>
Date: Mon, 13 Oct 2025 12:40:46 +0530
From: Himanshu Chauhan <hchauhan@...tanamicro.com>
To: Clément Léger <cleger@...osinc.com>
Cc: Paul Walmsley <pjw@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	Anup Patel <apatel@...tanamicro.com>, Xu Lu <luxu.kernel@...edance.com>, 
	Atish Patra <atishp@...shpatra.org>, Björn Töpel <bjorn@...osinc.com>, 
	Yunhui Cui <cuiyunhui@...edance.com>
Subject: Re: [PATCH v7 0/5] riscv: add support for SBI Supervisor Software Events

On Mon, Oct 13, 2025 at 12:23 PM Clément Léger <cleger@...osinc.com> wrote:
>
> Hi Paul,
>
> Thanks for caring about this series ;)
>
> On 10/10/2025 03:32, Paul Walmsley wrote:
> > Hi Clément,
> >
> > On Mon, 8 Sep 2025, Clément Léger wrote:
> >
> >> The SBI Supervisor Software Events (SSE) extensions provides a mechanism
> >> to inject software events from an SBI implementation to supervisor
> >> software such that it preempts all other supervisor level traps and
> >> interrupts. This extension is introduced by the SBI v3.0 specification[1].
> >>
> >> Various events are defined and can be send asynchronously to supervisor
> >> software (RAS, PMU, DEBUG, Asynchronous page fault) from SBI as well
> >> as platform specific events. Events can be either local (per-hart) or
> >> global. Events can be nested on top of each other based on priority and
> >> can interrupt the kernel at any time.
> >>
> >> First patch adds the SSE definitions. Second one adds support for SSE
> >> at arch level (entry code and stack allocations) and third one at driver
> >> level. Finally, the last patch add support for SSE events in the SBI PMU
> >> driver. Additional testing for that part is highly welcomed since there
> >> are a lot of possible path that needs to be exercised.
> >>
> >> Amongst the specific points that needs to be handle is the interruption
> >> at any point of the kernel execution and more specifically at the
> >> beginning of exception handling. Due to the fact that the exception entry
> >> implementation uses the SCRATCH CSR as both the current task struct and
> >> as the temporary register to switch the stack and save register, it is
> >> difficult to reliably get the current task struct if we get interrupted
> >> at this specific moment (ie, it might contain 0, the task pointer or tp).
> >> A fixup-like mechanism is not possible due to the nested nature of SSE
> >> which makes it really hard to obtain the original interruption site. In
> >> order to retrieve the task in a reliable manner, add an additional
> >> __sse_entry_task per_cpu array which stores the current task. Ideally,
> >> we would need to modify the way we retrieve/store the current task in
> >> exception handling so that it does not depend on the place where it's
> >> interrupted.
> >>
> >> Contrary to pseudo NMI [2], SSE does not modifies the way interrupts are
> >> handled and does not adds any overhead to existing code. Moreover, it
> >> provides "true" NMI-like interrupts which can interrupt the kernel at
> >> any time (even in exception handling). This is particularly crucial for
> >> RAS errors which needs to be handled as fast as possible to avoid any
> >> fault propagation.
> >>
> >> A test suite is available as a separate kselftest module. In order to
> >> build it, you can use the following command:
> >>
> >> $ KDIR=<build_dir> make O=build TARGETS="riscv/sse"-j $(($(nproc)-1)) -C tools/testing/selftests
> >>
> >> Then load the module using:
> >>
> >> $ sh run_sse_test.sh
> >>
> >> A KVM SBI SSE extension implementation is available at [2].
> >>
> >> Link: https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc7/riscv-sbi.pdf [1]
> >> Link: https://github.com/rivosinc/linux/tree/dev/cleger/sse_kvm [2]
> >
> > I updated these to apply on Linus' current master, commit 5472d60c129f,
> > cleaned up the checkpatch.pl --strict issues, applied Anup's pr_info()
> > suggestion, and pushed them up here to make it convenient for folks to
> > integrate and test:
> >
> >   https://git.kernel.org/pub/scm/linux/kernel/git/pjw/riscv.git/?h=riscv-experimental-for-v6.18
> >
> > Am assuming you didn't have other changes that you wanted to make; let me
> > know if that's not the case.
>
> Indeed, I do not have pending modification for this series. The KVM SBI
> SSE support will be submitted later that year.

I am testing this series with my RAS patch set. Will update on this.

Thanks
Regards
Himanshu

>
> >
> > I noticed that you asked for folks to do additional testing, particularly
> > of the SBI PMU driver integration, but didn't notice any additional
> > Tested-by:s.  It would be great if other folks on the list could do some
> > focused testing now, particularly since we're on v7 of this series, and
> > I'm sure others care about this.
>
>  I would have prefer a bit more reviews and testing before going through
> since SSE can be quite intrusive at execution time (even though the
> classic IRQ path should not be impacted, I expect mostly feedback/bugs
> from the SSE handling path itself). We'll see in a few days if people
> find such problems.
>
> Thanks,
>
> Clément
>
>
> >
> >
> > thanks,
> >
> > - Paul
> >
>

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