lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <01122bf2-7f8c-4d93-9557-c625b4eac631@oss.qualcomm.com>
Date: Mon, 13 Oct 2025 10:19:03 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Md Sadre Alam <quic_mdalam@...cinc.com>, broonie@...nel.org,
        robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
        andersson@...nel.org, konradybcio@...nel.org, vkoul@...nel.org,
        linux-arm-msm@...r.kernel.org, linux-spi@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        dmaengine@...r.kernel.org
Cc: quic_varada@...cinc.com
Subject: Re: [PATCH v2 4/9] arm64: dts: qcom: ipq5424: Add QPIC SPI NAND
 controller support

On 10/13/25 8:10 AM, Md Sadre Alam wrote:
> 
> 
> On 10/8/2025 6:00 PM, Konrad Dybcio wrote:
>> On 10/8/25 11:04 AM, Md Sadre Alam wrote:
>>> Add device tree nodes for QPIC SPI NAND flash controller support
>>> on IPQ5424 SoC.
>>>
>>> The IPQ5424 SoC includes a QPIC controller that supports SPI NAND flash
>>> devices with hardware ECC capabilities and DMA support through BAM
>>> (Bus Access Manager).
>>>
>>> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
>>> ---

[...]

>>
>>> +            dmas = <&qpic_bam 0>,
>>> +                   <&qpic_bam 1>,
>>> +                   <&qpic_bam 2>;
>>> +            dma-names = "tx", "rx", "cmd";
>>> +            status = "disabled";
>>
>> Is there anything preventing us from enabling both these nodes by
>> default on all boards (maybe secure configuration or required
>> regulators)?
> We can't enable NAND by default in the common DTSI because the GPIOs are shared between eMMC and NAND.The decision to enable NAND must be made at the board-specific level, depending on the flash type used on that
> particular board or RDP.Enabling it globally could lead to conflicts on platforms where eMMC is present.

Right, thanks

Konrad

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ