linux-kernel - Re: [PATCH net] net: ti: icssg-prueth: Fix fdb hash size configuration

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Message-ID: <aOzqMj1TbzJCZrRk@horms.kernel.org>
Date: Mon, 13 Oct 2025 13:01:54 +0100
From: Simon Horman <horms@...nel.org>
To: Meghana Malladi <m-malladi@...com>
Cc: pabeni@...hat.com, kuba@...nel.org, edumazet@...gle.com,
	davem@...emloft.net, andrew+netdev@...n.ch,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, srk@...com,
	Vignesh Raghavendra <vigneshr@...com>,
	Roger Quadros <rogerq@...nel.org>, danishanwar@...com
Subject: Re: [PATCH net] net: ti: icssg-prueth: Fix fdb hash size
 configuration

On Mon, Oct 13, 2025 at 02:29:25PM +0530, Meghana Malladi wrote:
> The ICSSG driver does the initial FDB configuration which
> includes setting the control registers. Other run time
> management like learning is managed by the PRU's. The default
> FDB hash size used by the firmware is 512 slots which is not
> aligned with the driver's configuration. Update the driver
> FDB config to fix it.
> 
> Fixes: abd5576b9c57f ("net: ti: icssg-prueth: Add support for ICSSG switch firmware")
> Signed-off-by: Meghana Malladi <m-malladi@...com>
> ---
> 
> Please refer trm [1] 6.4.14.12.17 section
> on how the FDB config register gets configured.
> 
> [1]: https://www.ti.com/lit/pdf/spruim2

Thanks for the link!
And thanks to TI for publishing this document.

> 
>  drivers/net/ethernet/ti/icssg/icssg_config.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.c b/drivers/net/ethernet/ti/icssg/icssg_config.c
> index da53eb04b0a4..3f8237c17d09 100644
> --- a/drivers/net/ethernet/ti/icssg/icssg_config.c
> +++ b/drivers/net/ethernet/ti/icssg/icssg_config.c
> @@ -66,6 +66,9 @@
>  #define FDB_GEN_CFG1		0x60
>  #define SMEM_VLAN_OFFSET	8
>  #define SMEM_VLAN_OFFSET_MASK	GENMASK(25, 8)
> +#define FDB_HASH_SIZE_MASK	GENMASK(6, 3)
> +#define FDB_HASH_SIZE_SHIFT	3
> +#define FDB_HASH_SIZE		3

I am slightly confused about this.

The patch description says "The default FDB hash size used by the firmware
is 512 slots which is not aligned with the driver's configuration."
And above FDB_HASH_SIZE is 3, which is the value that the driver will
now set hash size to.

But table 6-1404 (on page 4049) of [1] describes 3 as setting
the FDB hash size to 512 slots. I would have expected a different
value based on my understanding of the patch description.

>  
>  #define FDB_GEN_CFG2		0x64
>  #define FDB_VLAN_EN		BIT(6)
> @@ -463,6 +466,8 @@ void icssg_init_emac_mode(struct prueth *prueth)
>  	/* Set VLAN TABLE address base */
>  	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
>  			   addr <<  SMEM_VLAN_OFFSET);
> +	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
> +			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
>  	/* Set enable VLAN aware mode, and FDBs for all PRUs */
>  	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, (FDB_PRU0_EN | FDB_PRU1_EN | FDB_HOST_EN));
>  	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +
> @@ -484,6 +489,8 @@ void icssg_init_fw_offload_mode(struct prueth *prueth)
>  	/* Set VLAN TABLE address base */
>  	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK,
>  			   addr <<  SMEM_VLAN_OFFSET);
> +	regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, FDB_HASH_SIZE_MASK,
> +			   FDB_HASH_SIZE << FDB_HASH_SIZE_SHIFT);
>  	/* Set enable VLAN aware mode, and FDBs for all PRUs */
>  	regmap_write(prueth->miig_rt, FDB_GEN_CFG2, FDB_EN_ALL);
>  	prueth->vlan_tbl = (struct prueth_vlan_tbl __force *)(prueth->shram.va +
> 
> base-commit: 68a052239fc4b351e961f698b824f7654a346091
> -- 
> 2.43.0
>