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Message-ID: <20251014-qcom_ipq5424_nsscc-v7-4-081f4956be02@quicinc.com>
Date: Tue, 14 Oct 2025 22:35:29 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette
<mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"Varadarajan
Narayanan" <quic_varada@...cinc.com>,
Rob Herring <robh@...nel.org>,
"Krzysztof Kozlowski" <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
"Anusha Rao" <quic_anusha@...cinc.com>,
Devi Priya
<quic_devipriy@...cinc.com>,
Manikanta Mylavarapu
<quic_mmanikan@...cinc.com>,
Georgi Djakov <djakov@...nel.org>,
Philipp Zabel
<p.zabel@...gutronix.de>,
Richard Cochran <richardcochran@...il.com>,
Konrad
Dybcio <konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org>,
<devicetree@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<netdev@...r.kernel.org>, <quic_kkumarcs@...cinc.com>,
<quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
<quic_pavir@...cinc.com>, <quic_suruchia@...cinc.com>,
Luo Jie <quic_luoj@...cinc.com>,
Konrad Dybcio
<konrad.dybcio@....qualcomm.com>
Subject: [PATCH v7 04/10] clk: qcom: gcc-ipq5424: Enable NSS NoC clocks to
use icc-clk
Add NSS NoC clocks using the icc-clk framework to create interconnect
paths. The network subsystem (NSS) can be connected to these NoCs.
Additionally, add the LPASS CNOC and SNOC nodes to establish the complete
interconnect path.
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
---
drivers/clk/qcom/gcc-ipq5424.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c
index 71afa1b86b72..6cfe4f2b2888 100644
--- a/drivers/clk/qcom/gcc-ipq5424.c
+++ b/drivers/clk/qcom/gcc-ipq5424.c
@@ -3250,6 +3250,16 @@ static const struct qcom_icc_hws_data icc_ipq5424_hws[] = {
{ MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
{ MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_CNOC_PCIE3_2LANE_S_CLK },
{ MASTER_CNOC_USB, SLAVE_CNOC_USB, GCC_CNOC_USB_CLK },
+ { MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
+ { MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
+ { MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
+ { MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
+ { MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
+ { MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
+ { MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
+ { MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
+ { MASTER_CNOC_LPASS_CFG, SLAVE_CNOC_LPASS_CFG, GCC_CNOC_LPASS_CFG_CLK },
+ { MASTER_SNOC_LPASS, SLAVE_SNOC_LPASS, GCC_SNOC_LPASS_CLK },
};
static const struct of_device_id gcc_ipq5424_match_table[] = {
--
2.34.1
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