linux-kernel - [PATCH v7 06/10] clk: qcom: gcc-ipq5424: Add gpll0_out

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Message-ID: <20251014-qcom_ipq5424_nsscc-v7-6-081f4956be02@quicinc.com>
Date: Tue, 14 Oct 2025 22:35:31 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        "Varadarajan
 Narayanan" <quic_varada@...cinc.com>,
        Rob Herring <robh@...nel.org>,
        "Krzysztof Kozlowski" <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        "Anusha Rao" <quic_anusha@...cinc.com>,
        Devi Priya
	<quic_devipriy@...cinc.com>,
        Manikanta Mylavarapu
	<quic_mmanikan@...cinc.com>,
        Georgi Djakov <djakov@...nel.org>,
        Philipp Zabel
	<p.zabel@...gutronix.de>,
        Richard Cochran <richardcochran@...il.com>,
        Konrad
 Dybcio <konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski@...aro.org>,
        <devicetree@...r.kernel.org>, <linux-pm@...r.kernel.org>,
        <netdev@...r.kernel.org>, <quic_kkumarcs@...cinc.com>,
        <quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
        <quic_pavir@...cinc.com>, <quic_suruchia@...cinc.com>,
        Luo Jie <quic_luoj@...cinc.com>,
        Konrad Dybcio
	<konrad.dybcio@....qualcomm.com>
Subject: [PATCH v7 06/10] clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock

The clock gpll0_out_aux acts as the parent clock for some of the NSS
(Network Subsystem) clocks.

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
---
 drivers/clk/qcom/gcc-ipq5424.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c
index 6cfe4f2b2888..35af6ffeeb85 100644
--- a/drivers/clk/qcom/gcc-ipq5424.c
+++ b/drivers/clk/qcom/gcc-ipq5424.c
@@ -79,6 +79,20 @@ static struct clk_fixed_factor gpll0_div2 = {
 	},
 };
 
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+	.offset = 0x20000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.width = 4,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "gpll0_out_aux",
+		.parent_hws = (const struct clk_hw *[]) {
+			&gpll0.clkr.hw
+		},
+		.num_parents = 1,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+	},
+};
+
 static struct clk_alpha_pll gpll2 = {
 	.offset = 0x21000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
@@ -2934,6 +2948,7 @@ static struct clk_regmap *gcc_ipq5424_clocks[] = {
 	[GPLL2] = &gpll2.clkr,
 	[GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
 	[GPLL4] = &gpll4.clkr,
+	[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq5424_resets[] = {

-- 
2.34.1