linux-kernel - Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC

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Message-ID: <305fb869-c35d-4de8-bdd8-175fccc26137@oss.qualcomm.com>
Date: Tue, 14 Oct 2025 22:13:56 +0530
From: Taniya Das <taniya.das@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
        Jingyi Wang <jingyi.wang@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        aiqun.yu@....qualcomm.com, tingwei.zhang@....qualcomm.com,
        trilok.soni@....qualcomm.com, yijie.yang@....qualcomm.com,
        Tengfei Fan <tengfei.fan@....qualcomm.com>
Subject: Re: [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC



On 9/25/2025 8:52 AM, Dmitry Baryshkov wrote:
> On Wed, Sep 24, 2025 at 05:17:19PM -0700, Jingyi Wang wrote:
>> Kaanapali is Snapdragon SoC from Qualcomm.
>>
>> Features added in this patch:
>> - CPUs with PSCI idle states and cpufreq
>> - Interrupt-controller with PDC wakeup support
>> - Timers, TCSR Clock Controllers
>> - Reserved Shared memory
>> - GCC and RPMHCC
>> - TLMM
>> - Interconnect with CPU BWMONs
>> - QuP with uart
>> - SMMU
>> - RPMHPD
>> - UFS with Inline Crypto Engine
>> - LLCC
>> - Watchdog
>>
>> Written with help from Raviteja Laggyshetty(added interconnect nodes),
>> Taniya Das(added Clock Controllers and cpufreq), Jishnu Prakash
>> (added rpmhpd), Nitin Rawat(added ufs) and Gaurav Kashyap(added ICE).
>>
>> Co-developed-by: Tengfei Fan <tengfei.fan@....qualcomm.com>
>> Signed-off-by: Tengfei Fan <tengfei.fan@....qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1320 +++++++++++++++++++++++++++++++
>>  1 file changed, 1320 insertions(+)
>>
>> +
>> +	soc: soc@0 {
>> +		compatible = "simple-bus";
>> +
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		dma-ranges = <0 0 0 0 0x10 0>;
>> +		ranges = <0 0 0 0 0x10 0>;
>> +
>> +		gcc: clock-controller@...000 {
>> +			compatible = "qcom,kaanapali-gcc";
>> +			reg = <0x0 0x00100000 0x0 0x1f4200>;
>> +
>> +			clocks = <&bi_tcxo_div2>,
>> +				 <0>,
>> +				 <&sleep_clk>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>,
>> +				 <0>;
> 
> You have UFS clocks. Why are they <0> here?

Yeah Dmitry, I will update the ufs_mem_phy clocks in the next patch.

> 
>> +
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +			#power-domain-cells = <1>;
>> +		};
>> +
> 

-- 
Thanks,
Taniya Das