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Message-ID: <20251014191121.368475-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 14 Oct 2025 20:11:19 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>
Cc: linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 0/2] Add support for configuring pin properties on RZ/T2H-N2H SoCs
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Hi all,
This patch series adds support for configuring pin properties on the
Renesas RZ/T2H-N2H SoCs. The RZ/T2H allows configuring pin properties
through the DRCTLm (I/O Buffer Function Switching) registers, including:
- Drive strength (low/middle/high/ultra high)
- Pull-up/pull-down/no-bias configuration (3 options: no pull, pull-up,
pull-down)
- Schmitt trigger control (enable/disable)
- Slew rate control (2 options: slow/fast)
Cheers,
Prabhakar
Lad Prabhakar (2):
dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration
properties
pinctrl: renesas: rzt2h: Add pin configuration support
.../pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +
drivers/pinctrl/renesas/pinctrl-rzt2h.c | 230 ++++++++++++++++++
2 files changed, 243 insertions(+)
--
2.43.0
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