Message-ID: <77678dd6-071b-4911-a5c5-f1519c92e91a@tuxon.dev>
Date: Tue, 14 Oct 2025 11:36:27 +0300
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Philipp Zabel <p.zabel@...gutronix.de>, vkoul@...nel.org,
 kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 geert+renesas@...der.be, magnus.damm@...il.com,
 yoshihiro.shimoda.uh@...esas.com, biju.das.jz@...renesas.com
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
 Claudiu Beznea <claudiu.beznea.uj@...renesas.com>,
 Wolfram Sang <wsa+renesas@...g-engineering.com>
Subject: Re: [PATCH v7 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB
 PWRRDY

Hi, Philipp,

On 10/13/25 17:57, Philipp Zabel wrote:
> Hi Claudiu,
> 
> On Fr, 2025-10-10 at 14:26 +0300, Claudiu Beznea wrote:
>> Hi, Philipp,
>>
>> On 10/8/25 15:16, Claudiu Beznea wrote:
>>> Hi, Philipp,
>>>
>>> On 10/8/25 13:23, Philipp Zabel wrote:
>>>> Hi Claudiu,
>>>>
>>>> On Mi, 2025-10-08 at 12:29 +0300, Claudiu Beznea wrote:
>>>>> Hi, Philipp,
>>>>>
>>>>> On 10/8/25 11:34, Philipp Zabel wrote:
>>>>>> Hi Claudiu,
>>>>>>
>>>>>> On Do, 2025-09-25 at 13:02 +0300, Claudiu wrote:
>>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>>>>>>>
>>>>>>> On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called
>>>>>>> PWRRDY. This signal is managed by the system controller and must be
>>>>>>> de-asserted after powering on the area where USB PHY resides and asserted
>>>>>>> before powering it off.
>>>>>>>
>>>>>>> On power-on the USB PWRRDY signal need to be de-asserted before enabling
>>>>>>> clock and switching the module to normal state (through MSTOP support). The
>>>>>>> power-on configuration sequence
>>>>>> The wording makes me wonder, have you considered implementing this as a
>>>>>> power sequencing driver?
>>>>> No, haven't tried as power sequencing. At the moment this was started I
>>>>> think the power sequencing support wasn't merged.
>>>>>
>>>>> The approaches considered were:
>>>>> a/ power domain
>>>> Letting a power domain control a corresponding power ready signal would
>>>> have been my first instinct as well.
>>>>
>>>>> b/ regulator
>>>>> c/ as a reference counted bit done through regmap read/writes APIs
>>>>>
>>>>> a and b failed as a result of discussions in the previous posted versions.
>>>> Could you point me to the discussion related to a?
>>> It's this one
>>> https://lore.kernel.org/all/
>>> CAPDyKFrS4Dhd7DZa2zz=oPro1TiTJFix0awzzzp8Qatm-8Z2Ug@...l.gmail.com/
> 
> Thank you! From this discussion it still isn't clear to me whether
> Ulf's suggestion of using genpd on/off notifiers was considered and why

The genpd on/off notifier suggestion wasn't tried, but only the
implementation of PWRRDY handling through the power domain (what Ulf
suggested though "Move the entire reset handling into the PM domain
provider, as it obviously knows when the domain is getting turned on/off"
in
https://lore.kernel.org/all/fa9b3449-ea3e-4482-b7eb-96999445cea5@tuxon.dev/).
Sorry if I mislead you.

Ulf suggested then here
https://lore.kernel.org/all/CAPDyKFpLnREr4C=wZ7o8Lb-CZbQa4Nr2VTuYdZHZ26Rcb1Masg@mail.gmail.com/
that he is not agreeing anymore with having it as power domain due to the
discussion in thread
https://lore.kernel.org/all/TY3PR01MB1134652F9587CFA0ADE851CA486902@TY3PR01MB11346.jpnprd01.prod.outlook.com/
(I can't remember what made him taking back is ack on this solution and I
can't find something in the thread either).

If I'm not wrong, with the information that we have at the moment, the best
for the notifier would have to register it (before runtime resume) and
implement it in this driver (reset-rzg2l-usbphy-ctrl) so that, when the
pm_runtime_resume_and_get()/pm_runtime_put() in
rzg2l_usbphy_ctrl_probe()/rzg2l_usbphy_ctrl_remove() will be called (or
suspend/resume) the notifier will be called and set the PWRRDY bit. Please
let me know if you see it otherwise.

> it was dismissed.

The power domain approach was dismissed as a result of discussion from this
thread:
https://lore.kernel.org/all/TY3PR01MB1134652F9587CFA0ADE851CA486902@TY3PR01MB11346.jpnprd01.prod.outlook.com/

I don't remember exactly what triggered it and can't find it as well, sorry.

> 
> From the DT patches it looks like there is no actual separate power
> domain for USB, just the single always-on CPG power domain (in rzg2l-
> cpg.c). Is that correct?

That is correct, the CPG is a clock power domain. All the clocks that CPG
can be provided (including USB clocks) are part of CPG clock power domain.

> In the thread it sounded like there were
> multiple domains.

You probably refer to this:
https://lore.kernel.org/all/fa9b3449-ea3e-4482-b7eb-96999445cea5@tuxon.dev/

In there, I was trying to present to Ulf how I did implement (locally,
nothing posted) the handling of PWRRDY though power domains. In that case
the SYSC (System Controller), where the PWRRDY resides, was modeled as a
power domain, I passed to the reset-rzg2l-usbphy-ctrl DT node the phandle
to sysc USB power domain as:

power-domains = <&cpg R9A08G045_PD_USB_PHY>, <&sysc R9A08G045_SYSC_PD_USB>;

along with the cpg, and handled it in the reset-rzg2l-usbphy-ctrl probe().

> 
> Is the issue that you need the PWRRDY signal to be (de)asserted
> independently from the CPG power domain enable/disable?

Yes. I need to de-assert it before clocks, MSTOP on probe/resume and assert
it back after clocks, MSTOP, on remove/suspend.

> (Why?)

Due to hardware constraints. This is how Renesas HW team recommended.

> 
> Why can't the power domain provider (cpg) have the renesas,sysc-pwrrdy
> property and set the signal together with the power domain?

That can be done but, passing a SYSC phandle to the CPG DT node will not be
valid from the HW description point of view.

> 
>>>> I see v2 and v3 tried to control the bit from the PHY drivers, and in
>>>> v4 we were are already back to the reset driver.
>>> v2 passed the system controller (SYSC) phandle to the USB PHYs only (though
>>> renesas,sysc-signals DT property) where the PWRRDY bit was set. The PWRRDY
>>> bit was referenced counted in the SYSC driver though regmap APIs.
>>>
>>> v3 used the approach from v2 but passed the renesas,sysc-signals to all the
>>> USB related drivers.
>>>
>>> Then, in v4, the PWRRDY refcounting was dropped and passed
>>> renesas,sysc-signals only to the USB PHY CTRL DT node in the idea that this
>>> is the node that will always be probed first as all the other USB blocks
>>> need it and request resets from it.
>>>
>>> v5 and v6 kept the approach from v4 and only addressed misc comments or
>>> things that I noticed.
>>
>> Could you please let me know if you are OK with the approach proposed in
>> v7, so that I can start preparing a new version addressing your comments?
> 
> If the PWRRDY signal is an input to the USB2PHY control block, and not
> only to the PHY blocks, I have no issue with this being handled in the
> usb2phy reset driver -

Yes, this is how the Renesas HW team confirmed they are related.

> iff it is not sensible to just control the
> signal from the power domain driver.

As mentioned above, that can be done as well but, passing a SYSC phandle to
the CPG DT node will not be valid from the HW description point of view.

> 
> If we have to handle it in the reset driver, I'd prefer to see this
> controlled with a dev_pm_genpd_add_notifier(). If that is not possible,
> I'd like to understand why.

>From the code inspection I did, that can be done. From what I can tell at
the moment, I'll have to register a gepnd notifier from
reset-rzg2l-usbphy-ctrl, before runtime resuming the device and control the
SYSC PWRRDY from it.

Thank you,
Claudiu

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