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Message-ID: <aO4bWRqX_4rXud25@ryzen>
Date: Tue, 14 Oct 2025 11:43:53 +0200
From: Niklas Cassel <cassel@...nel.org>
To: Randolph Lin <randolph@...estech.com>
Cc: linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
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Subject: Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib
windows in glue driver
On Fri, Oct 03, 2025 at 10:35:23AM +0800, Randolph Lin wrote:
> The number of ob/ib windows is determined through write-read loops
> on registers in the core driver. Some glue drivers need to adjust
> the number of ob/ib windows to meet specific requirements,such as
Missing space after comma.
> hardware limitations. This change allows the glue driver to adjust
> the number of ob/ib windows to satisfy platform-specific constraints.
> The glue driver may adjust the number of ob/ib windows, but the values
> must stay within hardware limits.
Could we please get a better explaination than "satisfy platform-specific
constraints" ?
Your PCIe controller is synthesized with a certain number of {in,out}bound
windows, and I assume that dw_pcie_iatu_detect() correctly detects the number
of {in,out}bound windows, and initializes num_ob_windows/num_ib_windows
accordingly.
So, is the problem that because of some errata, you cannot use all the
{in,out}bound windows of the iATU?
Because it is hard to understand what kind of "hardware limit" that would
cause your SoC to not be able to use all the available {in,out}bound windows.
Because it is simply a mapping in the iATU (internal Address Translation Unit).
In fact, in many cases, e.g. the NVMe EPF driver, then number of {in,out}bound
windows is a major limiting factor of how many outstanding I/Os you can have,
so usually, you really want to be able to use the maximum that the hardware
supports.
TL;DR: to modify this common code, I think your reasoning has to be more
detailed.
Kind regards,
Niklas
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