linux-kernel - [PATCH 2/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes

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Message-ID: <1192765d18a1dd0886e2c5a7435dc0af922996ce.1760426064.git.adrianhoyin.ng@altera.com>
Date: Wed, 15 Oct 2025 10:12:43 +0800
From: adrianhoyin.ng@...era.com
To: robh@...nel.org,
	dinguyen@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: adrianhoyin.ng@...era.com
Subject: [PATCH 2/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes

From: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>

Add SMMU-V3 Performance Monitoring Counter Group (PMCG) nodes for
Agilex5 to support SMMU performance event monitoring.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 19f55a02bd56..633eab69e1c9 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -151,6 +151,12 @@ usbphy0: usbphy {
 		compatible = "usb-nop-xceiv";
 	};
 
+	pmu0: pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
 	soc: soc@0 {
 		compatible = "simple-bus";
 		ranges = <0 0 0 0xffffffff>;
@@ -840,5 +846,61 @@ queue7 {
 				};
 			};
 		};
+
+		pmu0_tcu: pmu@...02000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16002000 0x1000>,
+				<0x16022000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu0: pmu@...42000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16042000 0x1000>,
+				<0x16052000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu1: pmu@...62000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16062000 0x1000>,
+				<0x16072000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu2: pmu@...82000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x16082000 0x1000>,
+				<0x16092000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu3: pmu@...a2000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x160A2000 0x1000>,
+				<0x160B2000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu4: pmu@...c2000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x160C2000 0x1000>,
+				<0x160D2000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pmu0_tbu5: pmu@...e2000 {
+			compatible = "arm,smmu-v3-pmcg";
+			reg = <0x160E2000 0x1000>,
+				<0x160F2000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+		};
 	};
 };
-- 
2.49.GIT