linux-kernel - Re: [PATCH v2 1/7] dt-bindings: phy: spacemit: add SpacemiT PCIe/combo PHY

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Message-ID: <20251015145217.GA3554740-robh@kernel.org>
Date: Wed, 15 Oct 2025 09:52:17 -0500
From: Rob Herring <robh@...nel.org>
To: Alex Elder <elder@...cstar.com>
Cc: krzk+dt@...nel.org, conor+dt@...nel.org, bhelgaas@...gle.com,
	lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
	vkoul@...nel.org, kishon@...nel.org, dlan@...too.org,
	guodong@...cstar.com, pjw@...nel.org, palmer@...belt.com,
	aou@...s.berkeley.edu, alex@...ti.fr, p.zabel@...gutronix.de,
	christian.bruel@...s.st.com, shradha.t@...sung.com,
	krishna.chundru@....qualcomm.com, qiang.yu@....qualcomm.com,
	namcao@...utronix.de, thippeswamy.havalige@....com,
	inochiama@...il.com, devicetree@...r.kernel.org,
	linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
	spacemit@...ts.linux.dev, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/7] dt-bindings: phy: spacemit: add SpacemiT
 PCIe/combo PHY

On Mon, Oct 13, 2025 at 10:35:18AM -0500, Alex Elder wrote:
> Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in
> the SpacemiT K1 SoC.  This is one of three PCIe PHYs, and is unusual
> in that only the combo PHY can perform a calibration step needed to
> determine settings used by the other two PCIe PHYs.
> 
> Calibration must be done with the combo PHY in PCIe mode, and to allow
> this to occur independent of the eventual use for the PHY (PCIe or USB)
> some PCIe-related properties must be supplied: clocks; resets; and a
> syscon phandle.
> 
> Signed-off-by: Alex Elder <elder@...cstar.com>
> ---
> v2: - Added '>' to the description, and reworded it a bit
>     - Added an external oscillator clock, "refclk"
>     - Renamed the "global" reset to be "phy"
>     - Renamed a phandle property to be "spacemit,apmu"
>     - Dropped the label and status property from the example
> 
>  .../bindings/phy/spacemit,k1-combo-phy.yaml   | 114 ++++++++++++++++++
>  1 file changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
> new file mode 100644
> index 0000000000000..6e2f401b0ac27
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
> @@ -0,0 +1,114 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K1 PCIe/USB3 Combo PHY
> +
> +maintainers:
> +  - Alex Elder <elder@...cstar.com>
> +
> +description: >
> +  Of the three PHYs on the SpacemiT K1 SoC capable of being used for
> +  PCIe, one is a combo PHY that can also be configured for use by a
> +  USB 3 controller.  Using PCIe or USB 3 is a board design decision.
> +
> +  The combo PHY is also the only PCIe PHY that is able to determine
> +  PCIe calibration values to use, and this must be determined before
> +  the other two PCIe PHYs can be used.  This calibration must be
> +  performed with the combo PHY in PCIe mode, and is this is done
> +  when the combo PHY is probed.
> +
> +  The combo PHY uses an external oscillator as a reference clock.
> +  During normal operation, the PCIe or USB port driver is responsible
> +  for ensuring all other clocks needed by a PHY are enabled, and all
> +  resets affecting the PHY are deasserted.  However, for the combo
> +  PHY to perform calibration independent of whether it's later used
> +  for PCIe or USB, all PCIe mode clocks and resets must be defined.
> +
> +properties:
> +  compatible:
> +    const: spacemit,k1-combo-phy
> +
> +  reg:
> +    items:
> +      - description: PHY control registers
> +
> +  clocks:
> +    items:
> +      - description: External oscillator used by the PHY PLL
> +      - description: DWC PCIe Data Bus Interface (DBI) clock
> +      - description: DWC PCIe application AXI-bus Master interface clock
> +      - description: DWC PCIe application AXI-bus slave interface clock
> +
> +  clock-names:
> +    items:
> +      - const: refclk
> +      - const: dbi
> +      - const: mstr
> +      - const: slv
> +
> +  resets:
> +    items:
> +      - description: DWC PCIe Data Bus Interface (DBI) reset
> +      - description: DWC PCIe application AXI-bus Master interface reset
> +      - description: DWC PCIe application AXI-bus slave interface reset
> +      - description: PHY reset; must be deasserted for PHY to function
> +
> +  reset-names:
> +    items:
> +      - const: dbi
> +      - const: mstr
> +      - const: slv
> +      - const: phy

I think phy should be first as that's the main one to the phy and the 
others are somewhat questionable. Otherwise,

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>