linux-kernel - [tip: x86/microcode] x86/microcode/intel: Enable staging when available

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Message-ID: <176054713282.709179.14172574656114661140.tip-bot2@tip-bot2>
Date: Wed, 15 Oct 2025 16:52:12 -0000
From: "tip-bot2 for Chang S. Bae" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: "Chang S. Bae" <chang.seok.bae@...el.com>,
 "Borislav Petkov (AMD)" <bp@...en8.de>, Chao Gao <chao.gao@...el.com>,
 Tony Luck <tony.luck@...el.com>, Anselm Busse <abusse@...zon.de>,
 x86@...nel.org, linux-kernel@...r.kernel.org
Subject:
 [tip: x86/microcode] x86/microcode/intel: Enable staging when available

The following commit has been merged into the x86/microcode branch of tip:

Commit-ID:     bffeb2fd0b9c99d8af348da88335bff408c63882
Gitweb:        https://git.kernel.org/tip/bffeb2fd0b9c99d8af348da88335bff408c63882
Author:        Chang S. Bae <chang.seok.bae@...el.com>
AuthorDate:    Sun, 21 Sep 2025 15:48:41 -07:00
Committer:     Borislav Petkov (AMD) <bp@...en8.de>
CommitterDate: Wed, 15 Oct 2025 16:47:50 +02:00

x86/microcode/intel: Enable staging when available

With staging support implemented, enable it when the CPU reports the
feature.

  [ bp: Sort in the MSR properly. ]

Signed-off-by: Chang S. Bae <chang.seok.bae@...el.com>
Signed-off-by: Borislav Petkov (AMD) <bp@...en8.de>
Reviewed-by: Chao Gao <chao.gao@...el.com>
Reviewed-by: Tony Luck <tony.luck@...el.com>
Tested-by: Anselm Busse <abusse@...zon.de>
Link: https://lore.kernel.org/20250320234104.8288-1-chang.seok.bae@intel.com
---
 arch/x86/include/asm/msr-index.h      |  8 ++++++++
 arch/x86/kernel/cpu/microcode/intel.c | 17 +++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 2b4560b..2324ad7 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -166,6 +166,10 @@
 						 * Processor MMIO stale data
 						 * vulnerabilities.
 						 */
+#define ARCH_CAP_MCU_ENUM		BIT(16) /*
+						 * Indicates the presence of microcode update
+						 * feature enumeration and status information.
+						 */
 #define ARCH_CAP_FB_CLEAR		BIT(17)	/*
 						 * VERW clears CPU fill buffer
 						 * even on MDS_NO CPUs.
@@ -929,6 +933,10 @@
 #define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
 
 #define MSR_IA32_UCODE_WRITE		0x00000079
+
+#define MSR_IA32_MCU_ENUMERATION	0x0000007b
+#define MCU_STAGING			BIT(4)
+
 #define MSR_IA32_UCODE_REV		0x0000008b
 
 /* Intel SGX Launch Enclave Public Key Hash MSRs */
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index a42c5ef..8744f3a 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -983,6 +983,18 @@ static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c)
 	llc_size_per_core = (unsigned int)llc_size;
 }
 
+static __init bool staging_available(void)
+{
+	u64 val;
+
+	val = x86_read_arch_cap_msr();
+	if (!(val & ARCH_CAP_MCU_ENUM))
+		return false;
+
+	rdmsrq(MSR_IA32_MCU_ENUMERATION, val);
+	return !!(val & MCU_STAGING);
+}
+
 struct microcode_ops * __init init_intel_microcode(void)
 {
 	struct cpuinfo_x86 *c = &boot_cpu_data;
@@ -993,6 +1005,11 @@ struct microcode_ops * __init init_intel_microcode(void)
 		return NULL;
 	}
 
+	if (staging_available()) {
+		microcode_intel_ops.use_staging = true;
+		pr_info("Enabled staging feature.\n");
+	}
+
 	calc_llc_size_per_core(c);
 
 	return &microcode_intel_ops;