[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20251015030428.2980427-6-hongxing.zhu@nxp.com>
Date: Wed, 15 Oct 2025 11:04:22 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: frank.li@....com,
l.stach@...gutronix.de,
lpieralisi@...nel.org,
kwilczynski@...nel.org,
mani@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
bhelgaas@...gle.com,
shawnguo@...nel.org,
s.hauer@...gutronix.de,
kernel@...gutronix.de,
festevam@...il.com
Cc: linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
imx@...ts.linux.dev,
linux-kernel@...r.kernel.org,
Richard Zhu <hongxing.zhu@....com>
Subject: [PATCH v6 05/11] arm64: dts: imx8mq-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx8mq-evk matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index a88bc90346636..852992b915a39 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -375,6 +375,7 @@ &pcie0 {
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
vph-supply = <&vgen5_reg>;
+ supports-clkreq;
status = "okay";
};
@@ -398,6 +399,7 @@ &pcie1 {
<&clk IMX8MQ_CLK_PCIE2_AUX>;
vpcie-supply = <®_pcie1>;
vph-supply = <&vgen5_reg>;
+ supports-clkreq;
status = "okay";
};
--
2.37.1
Powered by blists - more mailing lists