linux-kernel - Re: [PATCH 05/19] sched/fair: Add LLC index mapping for CPUs

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Message-ID: <20251015110821.GP3289052@noisy.programming.kicks-ass.net>
Date: Wed, 15 Oct 2025 13:08:21 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Tim Chen <tim.c.chen@...ux.intel.com>
Cc: Ingo Molnar <mingo@...hat.com>,
	K Prateek Nayak <kprateek.nayak@....com>,
	"Gautham R . Shenoy" <gautham.shenoy@....com>,
	Vincent Guittot <vincent.guittot@...aro.org>,
	Juri Lelli <juri.lelli@...hat.com>,
	Dietmar Eggemann <dietmar.eggemann@....com>,
	Steven Rostedt <rostedt@...dmis.org>,
	Ben Segall <bsegall@...gle.com>, Mel Gorman <mgorman@...e.de>,
	Valentin Schneider <vschneid@...hat.com>,
	Madadi Vineeth Reddy <vineethr@...ux.ibm.com>,
	Hillf Danton <hdanton@...a.com>,
	Shrikanth Hegde <sshegde@...ux.ibm.com>,
	Jianyong Wu <jianyong.wu@...look.com>,
	Yangyu Chen <cyy@...self.name>,
	Tingyin Duan <tingyin.duan@...il.com>,
	Vern Hao <vernhao@...cent.com>, Len Brown <len.brown@...el.com>,
	Aubrey Li <aubrey.li@...el.com>, Zhao Liu <zhao1.liu@...el.com>,
	Chen Yu <yu.chen.surf@...il.com>, Chen Yu <yu.c.chen@...el.com>,
	Libo Chen <libo.chen@...cle.com>,
	Adam Li <adamli@...amperecomputing.com>,
	Tim Chen <tim.c.chen@...el.com>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 05/19] sched/fair: Add LLC index mapping for CPUs

On Sat, Oct 11, 2025 at 11:24:42AM -0700, Tim Chen wrote:
> Introduce an index mapping between CPUs and their LLCs. This provides

"Introduce a *dense* mapping ...", since we already have a mapping, but
as you explain below, that is sparse and not well suited for indexing.

> a continuous per LLC index needed for cache-aware load balancing in
> later patches.

> The maximum number of LLCs is limited by CONFIG_NR_LLCS. If the number
> of LLCs available exceeds CONFIG_NR_LLCS, the cache aware load balance
> is disabled. To further save memory, this array could be converted to
> dynamic allocation in the future, or the LLC index could be made NUMA
> node-wide.


> +config NR_LLCS
> +	int "Maximum number of Last Level Caches"
> +	range 2 1024
> +	depends on SMP && SCHED_CACHE
> +	default 64
> +	help
> +	  This allows you to specify the maximum number of last level caches
> +	  this kernel will support for cache aware scheduling.

Not really a fan of this max thing. I suppose I'll see the use in the
next few patches, but ideally we'd start with the dynamic solution.