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Message-ID: <202510162222.Fe1rY5aB-lkp@intel.com>
Date: Thu, 16 Oct 2025 22:47:55 +0800
From: kernel test robot <lkp@...el.com>
To: "Herve Codina (Schneider Electric)" <herve.codina@...tlin.com>,
Wolfram Sang <wsa-dev@...g-engineering.com>,
Jonathan Cameron <jic23@...nel.org>,
David Lechner <dlechner@...libre.com>,
Nuno Sá <nuno.sa@...log.com>,
Andy Shevchenko <andy@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>
Cc: llvm@...ts.linux.dev, oe-kbuild-all@...ts.linux.dev,
linux-iio@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Pascal Eberhard <pascal.eberhard@...com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH 2/4] iio: adc: Add support for the Renesas RZ/N1 ADC
Hi Herve,
kernel test robot noticed the following build errors:
[auto build test ERROR on jic23-iio/togreg]
[also build test ERROR on geert-renesas-devel/next linus/master v6.18-rc1 next-20251015]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Herve-Codina-Schneider-Electric/dt-bindings-iio-adc-Add-the-Renesas-RZ-N1-ADC/20251015-223254
base: https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link: https://lore.kernel.org/r/20251015142816.1274605-3-herve.codina%40bootlin.com
patch subject: [PATCH 2/4] iio: adc: Add support for the Renesas RZ/N1 ADC
config: hexagon-allmodconfig (https://download.01.org/0day-ci/archive/20251016/202510162222.Fe1rY5aB-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251016/202510162222.Fe1rY5aB-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510162222.Fe1rY5aB-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/iio/adc/rzn1-adc.c:243:35: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
243 | vc |= RZN1_ADC_VC_ADC1_ENABLE | RZN1_ADC_VC_ADC1_CHANNEL_SEL(adc1_ch);
| ^
drivers/iio/adc/rzn1-adc.c:53:42: note: expanded from macro 'RZN1_ADC_VC_ADC1_CHANNEL_SEL'
53 | #define RZN1_ADC_VC_ADC1_CHANNEL_SEL(_c) FIELD_PREP(RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK, _c)
| ^
>> drivers/iio/adc/rzn1-adc.c:304:16: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
304 | *adc1_data = RZN1_ADC_ADCX_GET_DATA(data_reg);
| ^
drivers/iio/adc/rzn1-adc.c:58:38: note: expanded from macro 'RZN1_ADC_ADCX_GET_DATA'
58 | #define RZN1_ADC_ADCX_GET_DATA(_reg) FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, _reg)
| ^
drivers/iio/adc/rzn1-adc.c:309:16: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
309 | *adc2_data = RZN1_ADC_ADCX_GET_DATA(data_reg);
| ^
drivers/iio/adc/rzn1-adc.c:58:38: note: expanded from macro 'RZN1_ADC_ADCX_GET_DATA'
58 | #define RZN1_ADC_ADCX_GET_DATA(_reg) FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, _reg)
| ^
3 errors generated.
vim +/FIELD_PREP +243 drivers/iio/adc/rzn1-adc.c
236
237 static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
238 int adc1_ch, int adc2_ch)
239 {
240 u32 vc = 0;
241
242 if (adc1_ch != -1)
> 243 vc |= RZN1_ADC_VC_ADC1_ENABLE | RZN1_ADC_VC_ADC1_CHANNEL_SEL(adc1_ch);
244
245 if (adc2_ch != -1)
246 vc |= RZN1_ADC_VC_ADC2_ENABLE | RZN1_ADC_VC_ADC2_CHANNEL_SEL(adc2_ch);
247
248 writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch));
249 }
250
251 static int rzn1_adc_vc_start_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
252 {
253 u32 val;
254
255 val = readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG);
256 if (val & RZN1_ADC_FORCE_VC(ch))
257 return -EBUSY;
258
259 writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG);
260
261 return 0;
262 }
263
264 static void rzn1_adc_vc_stop_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
265 {
266 writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG);
267 }
268
269 static int rzn1_adc_vc_wait_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
270 u32 *adc1_data, u32 *adc2_data)
271 {
272 u32 data_reg;
273 int ret;
274 u32 v;
275
276 /*
277 * When a VC is selected, it needs 20 ADC clocks to perform the
278 * conversion.
279 *
280 * The worst case is when the 16 VCs need to perform a conversion and
281 * our VC is the lowest in term of priority.
282 *
283 * In that case, the conversion is performed in 16 * 20 ADC clocks.
284 *
285 * The ADC clock can be set from 4MHz to 20MHz. This leads to a worst
286 * case of 16 * 20 * 1/4Mhz = 80us.
287 *
288 * Round it up to 100us
289 */
290
291 /*
292 * Wait for the ADC_FORCE_VC(n) to clear.
293 *
294 * On timeout, ret is -ETIMEDOUT, otherwise it will be 0.
295 */
296 ret = readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG,
297 v, !(v & RZN1_ADC_FORCE_VC(ch)),
298 0, 100);
299 if (ret)
300 return ret;
301
302 if (adc1_data) {
303 data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch));
> 304 *adc1_data = RZN1_ADC_ADCX_GET_DATA(data_reg);
305 }
306
307 if (adc2_data) {
308 data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch));
309 *adc2_data = RZN1_ADC_ADCX_GET_DATA(data_reg);
310 }
311
312 return 0;
313 }
314
--
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