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Message-ID: <202510161254.tQekPr3V-lkp@intel.com>
Date: Thu, 16 Oct 2025 13:20:54 +0800
From: kernel test robot <lkp@...el.com>
To: Elaine Zhang <zhangqing@...k-chips.com>, mturquette@...libre.com,
sboyd@...nel.org, sugar.zhang@...k-chips.com, heiko@...ech.de,
robh@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org
Cc: llvm@...ts.linux.dev, oe-kbuild-all@...ts.linux.dev,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, huangtao@...k-chips.com
Subject: Re: [PATCH v1 3/5] clk: rockchip: Add clock controller for the
RV1126B
Hi Elaine,
kernel test robot noticed the following build warnings:
[auto build test WARNING on rockchip/for-next]
[also build test WARNING on clk/clk-next pza/reset/next linus/master v6.18-rc1 next-20251015]
[cannot apply to pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Elaine-Zhang/clk-rockchip-Implement-rockchip_clk_register_armclk_v2/20251015-175108
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
patch link: https://lore.kernel.org/r/20251015091325.71333-4-zhangqing%40rock-chips.com
patch subject: [PATCH v1 3/5] clk: rockchip: Add clock controller for the RV1126B
config: arm-defconfig (https://download.01.org/0day-ci/archive/20251016/202510161254.tQekPr3V-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 39f292ffa13d7ca0d1edff27ac8fd55024bb4d19)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251016/202510161254.tQekPr3V-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510161254.tQekPr3V-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/clk/rockchip/clk-rv1126b.c:146:7: warning: unused variable 'mux_ddrphy_p' [-Wunused-const-variable]
146 | PNAME(mux_ddrphy_p) = { "dpll", "aclk_sysmem" };
| ^~~~~~~~~~~~
1 warning generated.
vim +/mux_ddrphy_p +146 drivers/clk/rockchip/clk-rv1126b.c
86
87 PNAME(mux_pll_p) = { "xin24m" };
88 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
89 PNAME(mux_gpll_aupll_p) = { "gpll", "aupll" };
90 PNAME(mux_gpll_aupll_cpll_p) = { "gpll", "aupll", "cpll" };
91 PNAME(mux_gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
92 PNAME(mux_cpll_24m_p) = { "cpll", "xin24m" };
93 PNAME(mux_24m_gpll_aupll_cpll_p) = { "xin24m", "gpll", "aupll", "cpll" };
94 PNAME(mux_24m_gpll_cpll_p) = { "xin24m", "gpll", "cpll" };
95 PNAME(mux_24m_gpll_aupll_p) = { "xin24m", "gpll", "aupll" };
96 PNAME(mux_sclk_uart_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2",
97 "clk_uart_frac0", "clk_uart_frac1" };
98 PNAME(mclk_sai0_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2",
99 "clk_audio_frac0", "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai0_from_io" };
100 PNAME(mclk_sai1_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", "clk_audio_frac0",
101 "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai1_from_io" };
102 PNAME(mclk_sai2_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", "clk_audio_frac0",
103 "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai2_from_io" };
104 PNAME(mux_sai_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", "clk_audio_frac0",
105 "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai0_from_io",
106 "mclk_sai1_from_io", "mclk_sai2_from_io"};
107 PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" };
108 PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" };
109 PNAME(mux_500m_400m_200m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div6" };
110 PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" };
111 PNAME(mux_500m_400m_300m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div4" };
112 PNAME(mux_333m_200m_p) = { "clk_cpll_div3", "clk_gpll_div6" };
113 PNAME(mux_600m_400m_200m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div6" };
114 PNAME(mux_400m_300m_200m_p) = { "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
115 PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_cpll_div10" };
116 PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" };
117 PNAME(mux_600m_24m_p) = { "clk_gpll_div2", "xin24m" };
118 PNAME(mux_armclk_p) = { "clk_core_pll", "clk_core_pvtpll" };
119 PNAME(aclk_npu_root_p) = { "clk_npu_pll", "clk_npu_pvtpll" };
120 PNAME(clk_saradc0_p) = { "clk_saradc0_src", "clk_saradc0_rcosc_io" };
121 PNAME(clk_core_vepu_p) = { "clk_vepu_pll", "clk_vepu_pvtpll" };
122 PNAME(clk_core_fec_p) = { "clk_core_fec_src", "clk_vcp_pvtpll" };
123 PNAME(clk_core_aisp_p) = { "clk_aisp_pll", "clk_vcp_pvtpll" };
124 PNAME(clk_core_isp_root_p) = { "clk_isp_pll", "clk_isp_pvtpll" };
125 PNAME(clk_gmac_ptp_ref_p) = { "clk_gmac_ptp_ref_src", "clk_gmac_ptp_from_io" };
126 PNAME(clk_saradc1_p) = { "clk_saradc1_src", "clk_saradc1_rcosc_io" };
127 PNAME(clk_saradc2_p) = { "clk_saradc2_src", "clk_saradc2_rcosc_io" };
128 PNAME(clk_rcosc_src_p) = { "xin24m", "clk_rcosc", "clk_rcosc_div2", "clk_rcosc_div3", "clk_rcosc_div4" };
129 PNAME(busclk_pmu_mux_p) = { "clk_cpll_div10", "clk_rcosc_src" };
130 PNAME(clk_xin_rc_div_p) = { "xin24m", "clk_rcosc_src" };
131 PNAME(clk_32k_p) = { "clk_xin_rc_div", "clk_32k_rtc", "clk_32k_io" };
132 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
133 PNAME(mux_24m_rcosc_buspmu_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src" };
134 PNAME(mux_24m_rcosc_buspmu_32k_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src", "clk_32k" };
135 PNAME(sclk_uart0_p) = { "sclk_uart0_src", "xin24m", "clk_rcosc_src" };
136 PNAME(clk_osc_rcosc_ctrl_p) = { "clk_rcosc_src", "clk_testout_out" };
137 PNAME(lrck_src_asrc_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3",
138 "fs_inter_from_sai0", "fs_inter_from_sai1", "fs_inter_from_sai2", "clkout_pdm"};
139 PNAME(clk_ref_pipephy_p) = { "clk_ref_pipephy_cpll_src", "xin24m" };
140 PNAME(clk_timer0_parents_p) = { "clk_timer_root", "mclk_sai0_from_io", "sclk_sai0_from_io" };
141 PNAME(clk_timer1_parents_p) = { "clk_timer_root", "mclk_sai1_from_io", "sclk_sai1_from_io" };
142 PNAME(clk_timer2_parents_p) = { "clk_timer_root", "mclk_sai2_from_io", "sclk_sai2_from_io" };
143 PNAME(clk_timer3_parents_p) = { "clk_timer_root", "mclk_asrc0", "mclk_asrc1" };
144 PNAME(clk_timer4_parents_p) = { "clk_timer_root", "mclk_asrc2", "mclk_asrc3" };
145 PNAME(clk_macphy_p) = { "xin24m", "clk_cpll_div20" };
> 146 PNAME(mux_ddrphy_p) = { "dpll", "aclk_sysmem" };
147 PNAME(clk_cpll_div10_p) = { "gpll", "clk_aisp_pll_src" };
148
--
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https://github.com/intel/lkp-tests/wiki
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