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Message-ID: <20251016052839.2650517-1-shubhrajyoti.datta@amd.com>
Date: Thu, 16 Oct 2025 10:58:39 +0530
From: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
To: <linux-edac@...r.kernel.org>
CC: <git@....com>, <shubhrajyoti.datta@...il.com>, <dan.carpenter@...aro.org>,
Michal Simek <michal.simek@....com>, Borislav Petkov <bp@...en8.de>, "Tony
Luck" <tony.luck@...el.com>, James Morse <james.morse@....com>, "Mauro
Carvalho Chehab" <mchehab@...nel.org>, Robert Richter <rric@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH] EDAC/versalnet: Refactor memory controller initialization and cleanup
Simplify the initialization and cleanup flow for Versal Net DDRMC
controllers in the EDAC driver. Key changes include:
* Introduced `init_single_versalnet()` for per-controller setup and
`init_versalnet()` for looping through NUM_CONTROLLERS.
* Added proper rollback logic using `remove_single_versalnet()` when
partial initialization fails.
* Improved readability and maintainability by reducing duplicated code and
consolidating error handling.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@....com>
---
drivers/edac/versalnet_edac.c | 158 +++++++++++++++++++---------------
1 file changed, 87 insertions(+), 71 deletions(-)
diff --git a/drivers/edac/versalnet_edac.c b/drivers/edac/versalnet_edac.c
index 1ded4c3f0213..fc7e4c43b387 100644
--- a/drivers/edac/versalnet_edac.c
+++ b/drivers/edac/versalnet_edac.c
@@ -758,92 +758,111 @@ static void versal_edac_release(struct device *dev)
kfree(dev);
}
-static int init_versalnet(struct mc_priv *priv, struct platform_device *pdev)
+static void remove_single_versalnet(struct mc_priv *priv, int i)
+{
+ struct mem_ctl_info *mci;
+
+ mci = priv->mci[i];
+ device_unregister(mci->pdev);
+ edac_mc_del_mc(mci->pdev);
+ edac_mc_free(mci);
+}
+
+static int init_single_versalnet(struct mc_priv *priv, struct platform_device *pdev, int i)
{
u32 num_chans, rank, dwidth, config;
- struct edac_mc_layer layers[2];
struct mem_ctl_info *mci;
+ struct edac_mc_layer layers[2];
struct device *dev;
enum dev_type dt;
char *name;
- int rc, i;
+ int rc;
- for (i = 0; i < NUM_CONTROLLERS; i++) {
- config = priv->adec[CONF + i * ADEC_NUM];
- num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
- rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
- dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
-
- switch (dwidth) {
- case XDDR5_BUS_WIDTH_16:
- dt = DEV_X16;
- break;
- case XDDR5_BUS_WIDTH_32:
- dt = DEV_X32;
- break;
- case XDDR5_BUS_WIDTH_64:
- dt = DEV_X64;
- break;
- default:
- dt = DEV_UNKNOWN;
- }
+ config = priv->adec[CONF + i * ADEC_NUM];
+ num_chans = FIELD_GET(MC5_NUM_CHANS_MASK, config);
+ rank = 1 << FIELD_GET(MC5_RANK_MASK, config);
+ dwidth = FIELD_GET(MC5_BUS_WIDTH_MASK, config);
+
+ switch (dwidth) {
+ case XDDR5_BUS_WIDTH_16:
+ dt = DEV_X16;
+ break;
+ case XDDR5_BUS_WIDTH_32:
+ dt = DEV_X32;
+ break;
+ case XDDR5_BUS_WIDTH_64:
+ dt = DEV_X64;
+ break;
+ default:
+ dt = DEV_UNKNOWN;
+ }
- if (dt == DEV_UNKNOWN)
- continue;
+ if (dt == DEV_UNKNOWN)
+ return 0;
- /* Find the first enabled device and register that one. */
- layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
- layers[0].size = rank;
- layers[0].is_virt_csrow = true;
- layers[1].type = EDAC_MC_LAYER_CHANNEL;
- layers[1].size = num_chans;
- layers[1].is_virt_csrow = false;
+ /* Find the first enabled device and register that one. */
+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+ layers[0].size = rank;
+ layers[0].is_virt_csrow = true;
+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
+ layers[1].size = num_chans;
+ layers[1].is_virt_csrow = false;
+
+ rc = -ENOMEM;
+ mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers,
+ sizeof(struct mc_priv));
+ if (!mci) {
+ edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
+ return rc;
+ }
+ priv->mci[i] = mci;
+ priv->dwidth = dt;
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return rc;
+ dev->release = versal_edac_release;
+ name = kmalloc(32, GFP_KERNEL);
+ sprintf(name, "versal-net-ddrmc5-edac-%d", i);
+ dev->init_name = name;
+ rc = device_register(dev);
+ if (rc)
+ goto err_mc_free;
- rc = -ENOMEM;
- mci = edac_mc_alloc(i, ARRAY_SIZE(layers), layers,
- sizeof(struct mc_priv));
- if (!mci) {
- edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i);
- goto err_alloc;
- }
+ mci->pdev = dev;
- priv->mci[i] = mci;
- priv->dwidth = dt;
+ platform_set_drvdata(pdev, priv);
- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
- dev->release = versal_edac_release;
- name = kmalloc(32, GFP_KERNEL);
- sprintf(name, "versal-net-ddrmc5-edac-%d", i);
- dev->init_name = name;
- rc = device_register(dev);
- if (rc)
- goto err_alloc;
+ mc_init(mci, dev);
+ rc = edac_mc_add_mc(mci);
+ if (rc) {
+ edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
+ goto err_unreg;
+ }
+ return 0;
+err_unreg:
+ device_unregister(mci->pdev);
+err_mc_free:
+ edac_mc_free(mci);
+ return rc;
+}
- mci->pdev = dev;
- platform_set_drvdata(pdev, priv);
+static int init_versalnet(struct mc_priv *priv, struct platform_device *pdev)
+{
+ int rc, i;
- mc_init(mci, dev);
- rc = edac_mc_add_mc(mci);
- if (rc) {
- edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\n", i);
- goto err_alloc;
- }
+ for (i = 0; i < NUM_CONTROLLERS; i++) {
+ rc = init_single_versalnet(priv, pdev, i);
+ if (rc)
+ goto err_rm_versalnet;
}
return 0;
-err_alloc:
- while (i--) {
- mci = priv->mci[i];
- if (!mci)
- continue;
-
- if (mci->pdev) {
- device_unregister(mci->pdev);
- edac_mc_del_mc(mci->pdev);
- }
-
- edac_mc_free(mci);
+err_rm_versalnet:
+ while (i) {
+ i--;
+ remove_single_versalnet(priv, i);
}
return rc;
@@ -857,9 +876,6 @@ static void remove_versalnet(struct mc_priv *priv)
for (i = 0; i < NUM_CONTROLLERS; i++) {
device_unregister(priv->mci[i]->pdev);
mci = edac_mc_del_mc(priv->mci[i]->pdev);
- if (!mci)
- return;
-
edac_mc_free(mci);
}
}
--
2.34.1
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