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Message-ID: <20251016202129.157614-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Thu, 16 Oct 2025 21:21:27 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Add Ethernet MAC (GMAC) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
The RZ/T2H integrates three GMAC interfaces based on the Synopsys
DesignWare MAC (version 5.20).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 445 +++++++++++++++++++++
1 file changed, 445 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index e397dd262c76..62499dca45ec 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -270,6 +270,444 @@ i2c2: i2c@...08000 {
status = "disabled";
};
+ gmac0: ethernet@...00000 {
+ compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x80100000 0 0x10000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 400>,
+ <&cpg CPG_CORE R9A09G077_CLK_PCLKH>,
+ <&cpg CPG_CORE R9A09G077_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 400>, <&cpg 401>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup0>;
+ snps,mtl-tx-config = <&mtl_tx_setup0>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup0: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup0: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac1: ethernet@...00000 {
+ compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x92000000 0 0x10000>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 416>,
+ <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
+ <&cpg CPG_CORE R9A09G077_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 416>, <&cpg 417>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup1>;
+ snps,mtl-tx-config = <&mtl_tx_setup1>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup1: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup1: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac2: ethernet@...10000 {
+ compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x92010000 0 0x10000>;
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 417>,
+ <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
+ <&cpg CPG_CORE R9A09G077_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 418>, <&cpg 419>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup2>;
+ snps,mtl-tx-config = <&mtl_tx_setup2>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio2: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup2: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup2: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
ethss: ethss@...10000 {
compatible = "renesas,r9a09g077-miic";
reg = <0 0x80110000 0 0x10000>;
@@ -429,6 +867,13 @@ sdhi1_vqmmc: vqmmc-regulator {
};
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <16 8 4 0 0 0 0>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
--
2.43.0
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