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Message-ID: <662a21a3-de8b-406f-a15d-b8a572aa79ab@oss.qualcomm.com>
Date: Thu, 16 Oct 2025 16:28:45 -0700
From: Vijay Kumar Tumati <vijay.tumati@....qualcomm.com>
To: Bryan O'Donoghue <bod@...nel.org>,
Hangxiang Ma <hangxiang.ma@....qualcomm.com>,
Loic Poulain <loic.poulain@....qualcomm.com>,
Robert Foss
<rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Todor Tomov <todor.too@...il.com>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: linux-i2c@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org, aiqun.yu@....qualcomm.com,
tingwei.zhang@....qualcomm.com, trilok.soni@....qualcomm.com,
yijie.yang@....qualcomm.com,
Jingyi Wang <jingyi.wang@....qualcomm.com>,
Atiya Kailany <atiya.kailany@....qualcomm.com>
Subject: Re: [PATCH v2 6/6] media: qcom: camss: vfe: Add support for VFE 1080
On 10/16/2025 3:54 AM, Bryan O'Donoghue wrote:
> On 16/10/2025 11:33, Hangxiang Ma wrote:
>>> But why ?
>>>
>>> ---
>>> bod
>> That a story. When testing the RDI path on Kaanapali, we found one image
>> buffer starved at 19/20 stage. We want to capture 20 images but only 19
>> received.
>>
>> On Kaanapali, the AUP and RUP are split into two separate registers not
>> a single one. Maybe this hardware change impacts something. Calling
>> ops->reg_update() in vfe_enable_output_v2 function only applies one
>> buffer address. The downstream code defers AUP and RUP to CSID
>> configuration stage. We mimic that and find it can solve this issue.
>>
>> ---
>> Hangxiang
>
> So this is the type of interesting detail that I'd go looking for in a
> commit log, a comment in the code or a footnote in the cover letter.
>
> One or two sentences in the commit log will do.
>
> ---
> bod
>
@Bryan, let me throw a bit more light here. I don't think the 19/20
buffers issue or the AUP-RUP register separation has anything to do
about this (at least not the first for sure). Fundamentally, on
Kaanapali architecture (or any architecture for that matter), the HW
guidance is to issue the reg_update (corresponding register write) after
all of the CSID configuration registers are written. It had always been
working for other chip sets to write to this register first and then
write the CSID registers but Kaanapali seems to have very strict
dependency in the hardware about this sequence and with the original
sequence, no RUP DONE or BUF DONE events are received at all. Hence the
need for this change. The 19/20 buffer issue that Hangxiang mentioned
about is a follow up of this where we enqueue two buffers to the RDI
write master from 'vfe_enable_output_v2()' but issue only one AUP update
after the CSID config. That was when we needed to add
'CAMSS_INIT_BUF_COUNT' and use consistently at both places. Hope this
makes sense now. Please let us know if you have any questions still.
Thank you.
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