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Message-Id: <20251016102020.3218579-9-wei.fang@nxp.com>
Date: Thu, 16 Oct 2025 18:20:19 +0800
From: Wei Fang <wei.fang@....com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
claudiu.manoil@....com,
vladimir.oltean@....com,
xiaoning.wang@....com,
Frank.Li@....com,
andrew+netdev@...n.ch,
davem@...emloft.net,
edumazet@...gle.com,
kuba@...nel.org,
pabeni@...hat.com,
richardcochran@...il.com
Cc: imx@...ts.linux.dev,
netdev@...r.kernel.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: [PATCH 8/8] arm64: dts: imx94: add basic NETC nodes and properties
Add ENETC, EMDIO and Timer support.
Note that this patch is for reference only. It will be removed once the
related dt-bindings patches have been reviewed.
Signed-off-by: Wei Fang <wei.fang@....com>
---
arch/arm64/boot/dts/freescale/imx94.dtsi | 118 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx943-evk.dts | 100 ++++++++++++++++
2 files changed, 218 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index d4a880496b0e..0527046601e5 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -1190,5 +1190,123 @@ wdog3: watchdog@...20000 {
status = "disabled";
};
};
+
+ netc_blk_ctrl: system-controller@...b0000 {
+ compatible = "nxp,imx94-netc-blk-ctrl";
+ reg = <0x0 0x4ceb0000 0x0 0x10000>,
+ <0x0 0x4cec0000 0x0 0x10000>,
+ <0x0 0x4c810000 0x0 0x7C>;
+ reg-names = "ierb", "prb", "netcmix";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&scmi_devpd IMX94_PD_NETC>;
+ status = "disabled";
+
+ netc_bus0: pcie@...00000 {
+ compatible = "pci-host-ecam-generic";
+ reg = <0x0 0x4ca00000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x0 0x0>;
+ msi-map = <0x00 &its 0x68 0x1>, //ENETC3 PF
+ <0x01 &its 0x61 0x1>, //Timer0
+ <0x02 &its 0x64 0x1>, //Switch
+ <0x40 &its 0x69 0x1>, //ENETC3 VF0
+ <0x80 &its 0x6a 0x1>, //ENETC3 VF1
+ <0xC0 &its 0x6b 0x1>; //ENETC3 VF2
+ /* Switch BAR0 - non-prefetchable memory */
+ ranges = <0x02000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0x80000
+ /* ENETC 3 and Timer 0 BAR0 - non-prefetchable memory */
+ 0x02000000 0x0 0x4cd40000 0x0 0x4cd40000 0x0 0x60000
+ /* Switch and Timer 0 BAR2 - prefetchable memory */
+ 0x42000000 0x0 0x4ce00000 0x0 0x4ce00000 0x0 0x20000
+ /* ENETC 3 VF0-2 BAR0 - non-prefetchable memory */
+ 0x02000000 0x0 0x4ce50000 0x0 0x4ce50000 0x0 0x30000
+ /* ENETC 3 VF0-2 BAR2 - prefetchable memory */
+ 0x42000000 0x0 0x4ce80000 0x0 0x4ce80000 0x0 0x30000>;
+
+ enetc3: ethernet@0,0 {
+ compatible = "pci1131,e110";
+ reg = <0x0 0 0 0 0>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2680>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ netc_timer0: ptp-timer@0,1 {
+ compatible = "pci1131,ee02";
+ reg = <0x100 0 0 0 0>;
+ status = "disabled";
+ };
+ };
+
+ netc_bus1: pcie@...00000 {
+ compatible = "pci-host-ecam-generic";
+ reg = <0x0 0x4cb00000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x1 0x1>;
+ msi-map = <0x100 &its 0x65 0x1>, //ENETC0 PF
+ <0x101 &its 0x62 0x1>, //Timer1
+ <0x140 &its 0x66 0x1>, //ENETC1 PF
+ <0x180 &its 0x67 0x1>, //ENETC2 PF
+ <0x181 &its 0x63 0x1>, //Timer2
+ <0x1C0 &its 0x60 0x1>; //EMDIO
+ /* ENETC 0-2 BAR0 - non-prefetchable memory */
+ ranges = <0x02000000 0x0 0x4cC80000 0x0 0x4cc80000 0x0 0xc0000
+ /* Timer 1-2 and EMDIO BAR0 - non-prefetchable memory */
+ 0x02000000 0x0 0x4cda0000 0x0 0x4cda0000 0x0 0x60000
+ /* Timer 1-2 and EMDIO BAR2 - prefetchable memory */
+ 0x42000000 0x0 0x4ce20000 0x0 0x4ce20000 0x0 0x30000>;
+
+ enetc0: ethernet@0,0 {
+ compatible = "pci1131,e101";
+ reg = <0x10000 0 0 0 0>;
+ status = "disabled";
+ };
+
+ netc_timer1: ptp-timer@0,1 {
+ compatible = "pci1131,ee02";
+ reg = <0x10100 0 0 0 0>;
+ status = "disabled";
+ };
+
+ enetc1: ethernet@8,0 {
+ compatible = "pci1131,e101";
+ reg = <0x14000 0 0 0 0>;
+ status = "disabled";
+ };
+
+ enetc2: ethernet@10,0 {
+ compatible = "pci1131,e101";
+ reg = <0x18000 0 0 0 0>;
+ status = "disabled";
+ };
+
+ netc_timer2: ptp-timer@10,1 {
+ compatible = "pci1131,ee02";
+ reg = <0x18100 0 0 0 0>;
+ status = "disabled";
+ };
+
+ netc_emdio: mdio@18,0 {
+ compatible = "pci1131,ee00";
+ reg = <0x1c000 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index c8c3eff9df1a..91c579ef31fe 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -12,6 +12,9 @@ / {
model = "NXP i.MX943 EVK board";
aliases {
+ ethernet0 = &enetc3;
+ ethernet1 = &enetc1;
+ ethernet2 = &enetc2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c5 = &lpi2c6;
@@ -127,6 +130,30 @@ memory@...00000 {
};
};
+&enetc1 {
+ clocks = <&scmi_clk IMX94_CLK_MAC4>;
+ clock-names = "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth3>;
+ phy-handle = <ðphy3>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc2 {
+ clocks = <&scmi_clk IMX94_CLK_MAC5>;
+ clock-names = "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth4>;
+ phy-handle = <ðphy4>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc3 {
+ status = "okay";
+};
+
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c3>;
@@ -396,6 +423,39 @@ &micfil {
status = "okay";
};
+&netc_blk_ctrl {
+ assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>,
+ <&scmi_clk IMX94_CLK_MAC5>;
+ assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>;
+ assigned-clock-rates = <250000000>, <250000000>;
+ status = "okay";
+};
+
+&netc_emdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emdio>;
+ status = "okay";
+
+ ethphy3: ethernet-phy@6 {
+ reg = <0x6>;
+ realtek,clkout-disable;
+ };
+
+ ethphy4: ethernet-phy@7 {
+ reg = <0x7>;
+ realtek,clkout-disable;
+ };
+};
+
+&netc_timer0 {
+ status = "okay";
+};
+
+&netc_timer1 {
+ status = "okay";
+};
+
&sai1 {
assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>,
@@ -431,6 +491,46 @@ &sai3 {
};
&scmi_iomuxc {
+ pinctrl_emdio: emdiogrp{
+ fsl,pins = <
+ IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x57e
+ IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x97e
+ >;
+ };
+
+ pinctrl_eth3: eth3grp {
+ fsl,pins = <
+ IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x51e
+ IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x51e
+ IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x51e
+ IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x51e
+ IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x51e
+ IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x59e
+ IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x51e
+ IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x59e
+ IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x51e
+ IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x51e
+ IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x51e
+ IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x51e
+ >;
+ };
+
+ pinctrl_eth4: eth4grp {
+ fsl,pins = <
+ IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x51e
+ IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x51e
+ IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x51e
+ IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x51e
+ IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x51e
+ IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x59e
+ IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x51e
+ IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x59e
+ IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x51e
+ IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x51e
+ IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x51e
+ IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x51e
+ >;
+ };
pinctrl_ioexpander_int2: ioexpanderint2grp {
fsl,pins = <
--
2.34.1
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