linux-kernel - Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib windows in glue driver

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Message-ID: <aPDc-yclubiHbUcD@ryzen>
Date: Thu, 16 Oct 2025 13:54:35 +0200
From: Niklas Cassel <cassel@...nel.org>
To: Randolph Lin <randolph@...estech.com>
Cc: linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
	linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
	jingoohan1@...il.com, mani@...nel.org, lpieralisi@...nel.org,
	kwilczynski@...nel.org, robh@...nel.org, bhelgaas@...gle.com,
	krzk+dt@...nel.org, conor+dt@...nel.org, alex@...ti.fr,
	aou@...s.berkeley.edu, palmer@...belt.com, paul.walmsley@...ive.com,
	ben717@...estech.com, inochiama@...il.com,
	thippeswamy.havalige@....com, namcao@...utronix.de,
	shradha.t@...sung.com, pjw@...nel.org, randolph.sklin@...il.com,
	tim609@...estech.com, Samuel Holland <samuel.holland@...ive.com>
Subject: Re: [PATCH v6 1/5] PCI: dwc: Allow adjusting the number of ob/ib
 windows in glue driver

Hello Randolph,

On Thu, Oct 16, 2025 at 07:12:36PM +0800, Randolph Lin wrote:
> > 
> > Could we please get a better explaination than "satisfy platform-specific
> > constraints" ?
> > 
> 
> Due to this SoC design, only iATU regions with mapped addresses within the
> 32-bits address range need to be programmed. However, this SoC has a design
> limitation in which the maximum region size supported by a single iATU
> entry is restricted to 4 GB, as it is based on a 32-bits address region.
> 
> For most EP devices, we can only define one entry in the "ranges" property
> of the devicetree that maps an address within the 32-bit range,
> as shown below:
> 	ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>;
> 
> For EP devices that require 64-bits address mapping (e.g., GPUs), BAR
> resources cannot be assigned.
> To support such devices, an additional entry for 64-bits address mapping is
> required, as shown below:
> 	ranges = <0x02000000 0x0 0x10000000 0x0 0x10000000 0x0 0xf0000000>,
> 		 <0x43000000 0x1 0x00000000 0x1 0x00000000 0x7 0x00000000>;
> 
> In the current common implementation, all ranges entries are programmed to
> the iATU. However, the size of entry for 64-bit address mapping exceeds the
> maximum region size that a single iATU entry can support. As a result, an
> error is reported during iATU programming, showing that the size of 64-bit
> address entry exceeds the region limit.

Note that each iATU can map up to IATU_LIMIT_ADDR_OFF_OUTBOUND_i +
IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_i.

Some DWC controllers have this at 4G, others have this at 8G.

Samuel has submitted a patch to use multiple iATUs to support
a window size larger than the iATU limit of a single iATU:
https://lore.kernel.org/linux-pci/aPDObXsvMoz1OYso@ryzen/T/#m11c3d95215982411d0bbd36940e70122b70ae820

Perhaps this patch could be of use for you too?


Kind regards,
Niklas