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Message-ID: <b4489d48-6ce3-4a48-a374-3852f4afc71e@oss.qualcomm.com>
Date: Thu, 16 Oct 2025 21:00:54 +0800
From: Wenmeng Liu <wenmeng.liu@....qualcomm.com>
To: Bryan O'Donoghue <bod@...nel.org>, Robert Foss <rfoss@...nel.org>,
Todor Tomov <todor.too@...il.com>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-media@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] media: dt-bindings: Add qcom,sm6150-camss
On 10/16/2025 6:43 PM, Bryan O'Donoghue wrote:
> On 16/10/2025 11:22, Wenmeng Liu wrote:
>> Add bindings for qcom,sm6150-camss in order to support the camera
>> subsystem found in Qualcomm Talos EVK board.
>
> Understood you are doing this to support the Talos EVK but the yaml
> should describe the specific SoC.
>
ACK>>
>> Signed-off-by: Wenmeng Liu <wenmeng.liu@....qualcomm.com>
>> ---
>> .../bindings/media/qcom,sm6150-camss.yaml | 283 +++++++++++
>> ++++++++++
>> 1 file changed, 283 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,sm6150-
>> camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm6150-
>> camss.yaml
>> new file mode 100644
>> index
>> 0000000000000000000000000000000000000000..758bed0970f2ceee7df30b579a0f60d583a9230c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,sm6150-camss.yaml
>> @@ -0,0 +1,283 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,sm6150-camss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SM6150 Camera Subsystem (CAMSS)
>> +
>> +maintainers:
>> + - Wenmeng Liu <wenmeng.liu@....qualcomm.com>
>> +
>> +description:
>> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sm6150-camss
>> +
>> + reg:
>> + maxItems: 9
>> +
>> + reg-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid_lite
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe_lite
>> +
>> + clocks:
>> + maxItems: 21
>> +
>> + clock-names:
>> + items:
>> + - const: camnoc_axi
>> + - const: cpas_ahb
>> + - const: csiphy0
>> + - const: csiphy0_timer
>> + - const: csiphy1
>> + - const: csiphy1_timer
>> + - const: csiphy2
>> + - const: csiphy2_timer
>> + - const: gcc_axi_hf
>> + - const: soc_ahb
>> + - const: vfe0
>> + - const: vfe0_axi
>> + - const: vfe0_cphy_rx
>> + - const: vfe0_csid
>> + - const: vfe1
>> + - const: vfe1_axi
>> + - const: vfe1_cphy_rx
>> + - const: vfe1_csid
>> + - const: vfe_lite
>> + - const: vfe_lite_cphy_rx
>> + - const: vfe_lite_csid
>> +
>> + interrupts:
>> + maxItems: 9
>> +
>> + interrupt-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid_lite
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe_lite
>> +
>> + interconnects:
>> + maxItems: 2
>> +
>> + interconnect-names:
>> + items:
>> + - const: ahb
>> + - const: hf_mnoc
>> +
>> + iommus:
>> + maxItems: 1
>> +
>> + power-domains:
>> + items:
>> + - description: IFE0 GDSC - Image Front End, Global Distributed
>> Switch Controller.
>> + - description: IFE1 GDSC - Image Front End, Global Distributed
>> Switch Controller.
>> + - description: Titan GDSC - Titan ISP Block, Global Distributed
>> Switch Controller.
>> +
>> + power-domain-names:
>> + items:
>> + - const: ife0
>> + - const: ife1
>> + - const: top
>> +
>> + vdd-csiphy-1p2-supply:
>> + description:
>> + Phandle to a 1.2V regulator supply to CSI PHYs.
>> +
>> + vdd-csiphy-1p8-supply:
>> + description:
>> + Phandle to 1.8V regulator supply to CSI PHYs pll block.
>> +
>> + ports:
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + description:
>> + CSI input ports.
>> +
>> + patternProperties:
>> + "^port@[0-2]+$":
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> +
>> + description:
>> + Input port for receiving CSI data from a CSIPHY.
>> +
>> + properties:
>> + endpoint:
>> + $ref: video-interfaces.yaml#
>> + unevaluatedProperties: false
>> +
>> + properties:
>> + data-lanes:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + required:
>> + - data-lanes
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - clocks
>> + - clock-names
>> + - interrupts
>> + - interrupt-names
>> + - interconnects
>> + - interconnect-names
>> + - iommus
>> + - power-domains
>> + - power-domain-names
>> + - vdd-csiphy-1p2-supply
>> + - vdd-csiphy-1p8-supply
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> + #include <dt-bindings/clock/qcom,qcs615-camcc.h>
>> + #include <dt-bindings/clock/qcom,qcs615-gcc.h>
>
> rpmh should come after qcs615.
>
ACK>> + #include <dt-bindings/interconnect/qcom,icc.h>
>> + #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + camss: isp@...3000 {
>> + compatible = "qcom,sm6150-camss";
>> +
>> + reg = <0x0 0x0acb3000 0x0 0x1000>,
>> + <0x0 0x0acba000 0x0 0x1000>,
>> + <0x0 0x0acc8000 0x0 0x1000>,
>> + <0x0 0x0ac65000 0x0 0x1000>,
>> + <0x0 0x0ac66000 0x0 0x1000>,
>> + <0x0 0x0ac67000 0x0 0x1000>,
>> + <0x0 0x0acaf000 0x0 0x4000>,
>> + <0x0 0x0acb6000 0x0 0x4000>,
>> + <0x0 0x0acc4000 0x0 0x4000>;
>> + reg-names = "csid0",
>> + "csid1",
>> + "csid_lite",
>> + "csiphy0",
>> + "csiphy1",
>> + "csiphy2",
>> + "vfe0",
>> + "vfe1",
>> + "vfe_lite";
>> +
>> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
>> + <&camcc CAM_CC_CPAS_AHB_CLK>,
>> + <&camcc CAM_CC_CSIPHY0_CLK>,
>> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
>> + <&camcc CAM_CC_CSIPHY1_CLK>,
>> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
>> + <&camcc CAM_CC_CSIPHY2_CLK>,
>> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
>> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
>> + <&camcc CAM_CC_SOC_AHB_CLK>,
>> + <&camcc CAM_CC_IFE_0_CLK>,
>> + <&camcc CAM_CC_IFE_0_AXI_CLK>,
>> + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
>> + <&camcc CAM_CC_IFE_0_CSID_CLK>,
>> + <&camcc CAM_CC_IFE_1_CLK>,
>> + <&camcc CAM_CC_IFE_1_AXI_CLK>,
>> + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
>> + <&camcc CAM_CC_IFE_1_CSID_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
>> +
>> + clock-names = "camnoc_axi",
>> + "cpas_ahb",
>> + "csiphy0",
>> + "csiphy0_timer",
>> + "csiphy1",
>> + "csiphy1_timer",
>> + "csiphy2",
>> + "csiphy2_timer",
>> + "gcc_axi_hf",
>> + "soc_ahb",
>> + "vfe0",
>> + "vfe0_axi",
>> + "vfe0_cphy_rx",
>> + "vfe0_csid",
>> + "vfe1",
>> + "vfe1_axi",
>> + "vfe1_cphy_rx",
>> + "vfe1_csid",
>> + "vfe_lite",
>> + "vfe_lite_cphy_rx",
>> + "vfe_lite_csid";
>> +
>> + interconnects = <&gem_noc MASTER_APPSS_PROC
>> QCOM_ICC_TAG_ACTIVE_ONLY
>> + &config_noc SLAVE_CAMERA_CFG
>> QCOM_ICC_TAG_ACTIVE_ONLY>,
>> + <&mmss_noc MASTER_CAMNOC_HF0
>> QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "ahb",
>> + "hf_mnoc";
>> +
>> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "csid0",
>> + "csid1",
>> + "csid_lite",
>> + "csiphy0",
>> + "csiphy1",
>> + "csiphy2",
>> + "vfe0",
>> + "vfe1",
>> + "vfe_lite";
>> +
>> + iommus = <&apps_smmu 0x820 0x40>;
>> +
>> + power-domains = <&camcc IFE_0_GDSC>,
>> + <&camcc IFE_1_GDSC>,
>> + <&camcc TITAN_TOP_GDSC>;
>> + power-domain-names = "ife0",
>> + "ife1",
>> + "top";
>> +
>> + vdd-csiphy-1p2-supply = <&vreg_l11a_1p2>;
>> + vdd-csiphy-1p8-supply = <&vreg_l12a_1p8>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + csiphy_ep0: endpoint {
>> + data-lanes = <0 1>;
>> + remote-endpoint = <&sensor_ep>;
>> + };
>> + };
>> + };
>> + };
>> + };
>>
>
will update in next version.
Thanks,
Wenmeng
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