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Message-ID: <gbwjh4tqaoxq2ng7moytv5vtalxpajdid5capjfqzare6dmphz@cmnv4p2q4eov>
Date: Thu, 16 Oct 2025 16:47:10 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Vikash Garodia <vikash.garodia@....qualcomm.com>
Cc: Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Bryan O'Donoghue <bod@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>, linux-arm-msm@...r.kernel.org,
linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Vishnu Reddy <quic_bvisredd@...cinc.com>
Subject: Re: [PATCH 5/8] media: iris: Move vpu register defines to common
header file
On Thu, Sep 25, 2025 at 04:44:43AM +0530, Vikash Garodia wrote:
> Some of vpu4 register defines are common with vpu3x. Move those into the
> common register defines header. This is done to reuse the defines for
> vpu4 in subsequent patch which enables the power sequence for vpu4.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@...cinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@...cinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@....qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
> .../platform/qcom/iris/iris_vpu_register_defines.h | 29 +++++++++++++++++
> 3 files changed, 29 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 339776a0b4672e246848c3a6a260eb83c7da6a60..0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -11,48 +11,12 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -#define AON_MVP_NOC_RESET 0x0001F000
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> #define CORE_CLK_RUN 0x0
> /* VPU v3.5 */
> #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
>
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> -#define CORE_BRIDGE_SW_RESET BIT(0)
> -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> -
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> -#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
>
> -#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
> -
> -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> -
> #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
> #define SW_RESET BIT(0)
> #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bbd999a41236dca5cf5700e452a6fed69f4fc922..a7b1fb8173e02d22e6f2af4ea170738c6408f65b 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -11,9 +11,6 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -
> #define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
>
> #define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
> @@ -38,10 +35,6 @@
> #define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
> #define HOST2XTENSA_INTR_ENABLE BIT(0)
>
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> #define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
> #define CPU_IC_SOFTINT_H2A_SHFT 0x0
>
> @@ -53,23 +46,7 @@
> #define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
> #define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
>
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -
> #define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
>
> static void iris_vpu_interrupt_init(struct iris_core *core)
> {
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..6474f561c8dc29d1975bb44792595d86f16b6cff 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -9,9 +9,38 @@
> #define VCODEC_BASE_OFFS 0x00000000
> #define CPU_BASE_OFFS 0x000A0000
> #define WRAPPER_BASE_OFFS 0x000B0000
> +#define AON_BASE_OFFS 0x000E0000
> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> +#define AON_MVP_NOC_RESET 0x0001F000
>
> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
>
> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
Registers here got totally unsorted (they were in the original source
file). Seeing this makes me sad.
> +
> +#define CORE_BRIDGE_SW_RESET BIT(0)
> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> +#define MSK_CORE_POWER_ON BIT(1)
> +#define CTL_AXI_CLK_HALT BIT(0)
> +#define CTL_CLK_HALT BIT(1)
> +#define REQ_POWER_DOWN_PREP BIT(0)
> +#define RESET_HIGH BIT(0)
> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
Ugh. This mixed all the bits, loosing connection between the register
and the corresponding bits. I'm going to pick up this patch into the
sc7280 series and I will improve it there, keeping the link between
registers and bit fields.
>
> #endif
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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