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Message-ID: <87plalzmg4.ffs@tglx>
Date: Fri, 17 Oct 2025 15:28:59 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Charles Mirabile <cmirabil@...hat.com>
Cc: alex@...ti.fr, aou@...s.berkeley.edu, cmirabil@...hat.com,
conor+dt@...nel.org, devicetree@...r.kernel.org, dramforever@...e.com,
krzk+dt@...nel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, lzampier@...hat.com, palmer@...belt.com,
paul.walmsley@...ive.com, robh@...nel.org, samuel.holland@...ive.com,
zhangxincheng@...rarisc.com
Subject: Re: [PATCH v5 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC
On Thu, Oct 16 2025 at 15:58, Charles Mirabile wrote:
> On Thu, Oct 16, 2025 at 07:53:26PM +0200, Thomas Gleixner wrote:
> What do you think about the attached patch (it should be not corrupt :^)
> I think I adressed your concerns, and I ran it through clang-format too.
>
> I folded everything into one diff for ease of review, but when we send it
> officially there will be a separate patch for the caching refactor.
Looks about right and it's a net win for everyone due to the suspend
path cleanup.
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