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Message-Id: <20251017-knp_video-v2-1-f568ce1a4be3@oss.qualcomm.com>
Date: Fri, 17 Oct 2025 19:46:22 +0530
From: Vikash Garodia <vikash.garodia@....qualcomm.com>
To: Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Bryan O'Donoghue <bod@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, linux-media@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Vishnu Reddy <quic_bvisredd@...cinc.com>,
Vikash Garodia <vikash.garodia@....qualcomm.com>
Subject: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add
kaanapali video codec binding
Kaanapali SOC brings in the new generation of video IP i.e iris4. When
compared to previous generation, iris3x, it has,
- separate power domains for stream and pixel processing hardware blocks
(bse and vpp).
- additional power domain for apv codec.
- power domains for individual pipes (VPPx).
- different clocks and reset lines.
Iommus include all the different stream-ids which can be possibly
generated by vpu4 video hardware in both secure and non secure execution
mode.
The vpu have reserved iova, i.e some portion of the addressable range is
reserved for IO registers. Iris_resv would describe the acceptable
address range.
Signed-off-by: Vikash Garodia <vikash.garodia@....qualcomm.com>
---
.../bindings/media/qcom,kaanapali-iris.yaml | 231 +++++++++++++++++++++
1 file changed, 231 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..39e9ac9dad2212e5ae8dc3d45e764418fe7d358d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
@@ -0,0 +1,231 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Kaanapali Iris video encoder and decoder
+
+maintainers:
+ - Vikash Garodia <vikash.garodia@....qualcomm.com>
+ - Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>
+
+description:
+ The iris video processing unit is a video encode and decode accelerator
+ present on Qualcomm Kaanapali SoC.
+
+properties:
+ compatible:
+ const: qcom,kaanapali-iris
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 10
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+ - const: iface1
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: vcodec_bse
+ - const: vcodec_vpp0
+ - const: vcodec_vpp1
+ - const: vcodec_apv
+
+ dma-coherent: true
+
+ firmware-name:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ minItems: 3
+ maxItems: 8
+
+ memory-region:
+ minItems: 1
+ maxItems: 2
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+ power-domains:
+ maxItems: 7
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mxc
+ - const: mmcx
+ - const: vpp0
+ - const: vpp1
+ - const: apv
+
+ resets:
+ maxItems: 4
+
+ reset-names:
+ items:
+ - const: bus0
+ - const: bus1
+ - const: core_freerun_reset
+ - const: vcodec0_core_freerun_reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dma-coherent
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - iommus
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@...0000 {
+ compatible = "qcom,kaanapali-iris";
+ reg = <0x02000000 0xf0000>;
+
+ clocks = <&gcc_video_axi0_clk>,
+ <&video_cc_mvs0c_clk>,
+ <&video_cc_mvs0_clk>,
+ <&gcc_video_axi1_clk>,
+ <&video_cc_mvs0c_freerun_clk>,
+ <&video_cc_mvs0_freerun_clk>,
+ <&video_cc_mvs0b_clk>,
+ <&video_cc_mvs0_vpp0_clk>,
+ <&video_cc_mvs0_vpp1_clk>,
+ <&video_cc_mvs0a_clk>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec_bse",
+ "vcodec_vpp0",
+ "vcodec_vpp1",
+ "vcodec_apv";
+
+ dma-coherent;
+
+ interconnects = <&gem_noc_master_appss_proc &config_noc_slave_venus_cfg>,
+ <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1940 0x0>,
+ <&apps_smmu 0x1944 0x0>,
+ <&apps_smmu 0x1a20 0x0>,
+ <&apps_smmu 0x1943 0x0>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ memory-region = <&video_mem>, <&iris_resv>;
+
+ power-domains = <&video_cc_mvs0c_gdsc>,
+ <&video_cc_mvs0_gdsc>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&video_cc_mvs0_vpp0_gdsc>,
+ <&video_cc_mvs0_vpp1_gdsc>,
+ <&video_cc_mvs0a_gdsc>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vpp0",
+ "vpp1",
+ "apv";
+
+ resets = <&gcc_video_axi0_clk_ares>,
+ <&gcc_video_axi1_clk_ares>,
+ <&video_cc_mvs0c_freerun_clk_ares>,
+ <&video_cc_mvs0_freerun_clk_ares>;
+ reset-names = "bus0",
+ "bus1",
+ "core_freerun_reset",
+ "vcodec0_core_freerun_reset";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000 533000000 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 630000000 630000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l0>,
+ <&rpmhpd_opp_turbo_l0>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 630000000 850000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
--
2.34.1
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