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Message-ID: <62nvkgq4f5hoew4lbvszizplkm67t67dbpskej3ha6m55jnblx@vajuvual7lng>
Date: Fri, 17 Oct 2025 15:54:09 -0700
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>, 
	Mani Chandana Ballary Kuntumalla <quic_mkuntuma@...cinc.com>, marijn.suijten@...ainline.org, swboyd@...omium.org, 
	mripard@...nel.org, abel.vesa@...aro.org, konradybcio@...nel.org, robh@...nel.org, 
	krzk+dt@...nel.org, conor+dt@...nel.org, robin.clark@....qualcomm.com, 
	jessica.zhang@....qualcomm.com, abhinav.kumar@...ux.dev, sean@...rly.run, airlied@...il.com, 
	simona@...ll.ch, alex.vinarskis@...il.com, linux-arm-msm@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, freedreno@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org, 
	quic_rajeevny@...cinc.com, quic_vproddut@...cinc.com, quic_riteshk@...cnic.com, 
	quic_amitsi@...cnic.com
Subject: Re: [PATCH 3/4] arm64: dts: qcom: lemans-ride: Enable dispcc1

On Wed, Oct 01, 2025 at 11:43:44AM +0200, Konrad Dybcio wrote:
> On 9/26/25 3:53 PM, Dmitry Baryshkov wrote:
> > On Fri, Sep 26, 2025 at 02:29:55PM +0530, Mani Chandana Ballary Kuntumalla wrote:
> >> This change enables display1 clock controller.
> >>
> >> Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@...cinc.com>
> >> ---
> >>  arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++++
> >>  1 file changed, 4 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
> >> index c69aa2f41ce2..d4436bc473ba 100644
> >> --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
> >> @@ -436,6 +436,10 @@ vreg_l8e: ldo8 {
> >>  	};
> >>  };
> >>  
> >> +&dispcc1 {
> >> +	status = "okay";
> > 
> > I think this one should be enabled by default. Unless Konrad or Bjorn
> > disagrees, please fix lemans.dtsi.
> 
> Of course there is no reason for clock controllers to be disabled
> 

On SC8280XP we have the same setup (two MDSS), there the clock
controller was left disabled because not all SKUs had that IP-block
accessible.

Whether this is the case of not for Lemans I don't know, if it is then
the commit message should have stated that.

Regards,
Bjorn

> Konrad

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