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Message-ID: <aPHj77kAxEmEEPmW@ninjato>
Date: Fri, 17 Oct 2025 08:36:31 +0200
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: "Herve Codina (Schneider Electric)" <herve.codina@...tlin.com>
Cc: Jonathan Cameron <jic23@...nel.org>,
	David Lechner <dlechner@...libre.com>,
	Nuno Sá <nuno.sa@...log.com>,
	Andy Shevchenko <andy@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Liam Girdwood <lgirdwood@...il.com>,
	Mark Brown <broonie@...nel.org>, linux-iio@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Pascal Eberhard <pascal.eberhard@...com>,
	Miquel Raynal <miquel.raynal@...tlin.com>,
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH 3/4] ARM: dts: renesas: r9a06g032: Add the ADC device

On Wed, Oct 15, 2025 at 04:28:15PM +0200, Herve Codina (Schneider Electric) wrote:
> The ADC available in the r9a06g032 SoC can use up to two internal ACD
> cores (ADC1 and ADC2) those internal cores are handled through ADC
> controller virtual channels.
> 
> Describe this device.
> 
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@...tlin.com>

Looks good given the current bindings. Despite clock-names will need an update:

Reviewed-by: Wolfram Sang <wsa+renesas@...g-engineering.com>


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