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Message-ID: <20251017084654.2929945-2-h-salunke@ti.com>
Date: Fri, 17 Oct 2025 14:16:52 +0530
From: Hrushikesh Salunke <h-salunke@...com>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>
CC: <s-vadapalli@...com>, <danishanwar@...com>,
<linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH 1/3] arm64: dts: ti: k3-j784s4-evm-pcie0-pcie1-ep: Add boot phase tag to "pcie1_ep"
J784S4 SoC has two instances of PCIe which are PCIe0 and PCIe1. J784S4
SoC uses PCIe1 instance for PCIe boot process. So it needs to be in
endpoint mode and it needs to be functional at all stages of PCIe boot
process. Thus add the "bootph-all" boot phase tag to "pcie1_ep" device
tree node.
Signed-off-by: Hrushikesh Salunke <h-salunke@...com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
index 685305092bd8..22533d678f79 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
@@ -75,5 +75,6 @@ pcie1_ep: pcie-ep@...0000 {
dma-coherent;
phys = <&serdes0_pcie1_link>;
phy-names = "pcie-phy";
+ bootph-all;
};
};
--
2.34.1
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