linux-kernel - Re: [PATCH v1 3/5] PCI: tegra: Use readl_poll

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Message-ID: <ose3ww7me26byqwsyk33tipylkx3kolnc3mjwrlmjwsmza2zf3@os7lkt4svaqi>
Date: Sun, 19 Oct 2025 13:20:36 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Anand Moon <linux.amoon@...il.com>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>, 
	Krzysztof Wilczyński <kwilczynski@...nel.org>, Rob Herring <robh@...nel.org>, 
	Bjorn Helgaas <bhelgaas@...gle.com>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Conor Dooley <conor+dt@...nel.org>, Thierry Reding <thierry.reding@...il.com>, 
	Jonathan Hunter <jonathanh@...dia.com>, 
	"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" <linux-pci@...r.kernel.org>, 
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, 
	"open list:TEGRA ARCHITECTURE SUPPORT" <linux-tegra@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>, 
	Mikko Perttunen <mperttunen@...dia.com>
Subject: Re: [PATCH v1 3/5] PCI: tegra: Use readl_poll_timeout() for link
 status polling

On Fri, Sep 26, 2025 at 12:57:44PM +0530, Anand Moon wrote:
> Replace the manual `do-while` polling loops with the readl_poll_timeout()
> helper when checking the link DL_UP and DL_LINK_ACTIVE status bits
> during link bring-up. This simplifies the code by removing the open-coded
> timeout logic in favor of the standard, more robust iopoll framework.
> The change improves readability and reduces code duplication.
> 
> Cc: Thierry Reding <thierry.reding@...il.com>
> Cc: Mikko Perttunen <mperttunen@...dia.com>
> Signed-off-by: Anand Moon <linux.amoon@...il.com>
> ---
> v1: dropped the include  <linux/iopoll.h> header file.
> ---
>  drivers/pci/controller/pci-tegra.c | 37 +++++++++++-------------------
>  1 file changed, 14 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 07a61d902eae..b0056818a203 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -2169,37 +2169,28 @@ static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
>  	value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
>  	writel(value, port->base + RP_PRIV_MISC);
>  
> -	do {
> -		unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
> +	while (retries--) {
> +		int err;
>  
> -		do {
> -			value = readl(port->base + RP_VEND_XP);
> -
> -			if (value & RP_VEND_XP_DL_UP)
> -				break;
> -
> -			usleep_range(1000, 2000);
> -		} while (--timeout);
> -
> -		if (!timeout) {
> +		err = readl_poll_timeout(port->base + RP_VEND_XP, value,
> +					 value & RP_VEND_XP_DL_UP,
> +					 1000,

The delay between the iterations had range of (1000, 2000), now it will become
(250, 1000). How can you ensure that this delay is sufficient?

- Mani

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