lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <6b9528bb-feee-4c6f-8d93-3bda1c4f7e96@kernel.org>
Date: Mon, 20 Oct 2025 10:22:55 -0500
From: Dinh Nguyen <dinguyen@...nel.org>
To: Khairul Anuar Romli <khairul.anuar.romli@...era.com>,
 Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>, Vinod Koul
 <vkoul@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>,
 "open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM"
 <dmaengine@...r.kernel.org>,
 "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
 <devicetree@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>,
 Miquel Raynal <miquel.raynal@...tlin.com>,
 Richard Weinberger <richard@....at>, Vignesh Raghavendra <vigneshr@...com>,
 Niravkumar L Rabara <niravkumar.l.rabara@...el.com>,
 "open list:CADENCE NAND DRIVER" <linux-mtd@...ts.infradead.org>,
 Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>
Subject: Re: [PATCH v3 0/3] Add iommu supports



On 10/14/25 19:13, Khairul Anuar Romli wrote:
> This patch series adds IOMMU support for the Agilex5 platform by:
> 
> - Updating the device tree bindings for:
>    - Cadence HP NAND controller (`cdns,hp-nfc`)
>    - Synopsys DesignWare AXI DMA controller (`snps,dw-axi-dmac`)
>    to accept the `iommus` property.
> 
> - Adding the SMMU (System Memory Management Unit) node to the Agilex5
>    device tree and wiring up the IOMMU properties to the supported
>    peripherals:
>    - NAND controller
>    - DMA controller
>    - SPI controller
> 
> The Agilex5 SoC includes an ARM SMMU v3 with dedicated Translation Buffer
> Units (TBUs) for peripherals. These allow for hardware-enforced DMA
> address translation and memory isolation using the IOMMU framework.
> 
> Enabling IOMMU support ensures proper integration of these devices in
> virtualized or secure environments, and aligns the platform with ARM’s
> architectural requirements.
> 
> ---
> Changes in v3:
> 	- Refined commit messages with detailed hardware descriptions.
> 	- Clarified which peripherals are covered in the DT changes.
> Changes in v2:
> 	- Add more description in the commit message body to clarify
> 	  device required for this changes.
> ---
> Khairul Anuar Romli (3):
>    dt-bindings: mtd: cdns,hp-nfc: Add iommu property
>    dt-bindings: dma: snps,dw-axi-dmac: Add iommu property
>    arm64: dts: socfpga: agilex5: Add SMMU nodes
> 

Applied!

Thanks,
Dinh

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ