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Message-ID: <20251020165152.666221-8-elder@riscstar.com>
Date: Mon, 20 Oct 2025 11:51:50 -0500
From: Alex Elder <elder@...cstar.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
dlan@...too.org
Cc: pjw@...nel.org,
palmer@...belt.com,
aou@...s.berkeley.edu,
alex@...ti.fr,
guodong@...cstar.com,
devicetree@...r.kernel.org,
spacemit@...ts.linux.dev,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 7/8] riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3
Define DTS nodes to enable support for QSPI on the K1 SoC, including
the pin control configuration used. Enable QSPI on the Banana Pi
BPI-F3 board.
Signed-off-by: Alex Elder <elder@...cstar.com>
---
.../boot/dts/spacemit/k1-bananapi-f3.dts | 6 ++++++
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 21 +++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 16 ++++++++++++++
3 files changed, 43 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 33ca816bfd4b3..2f3750f7fd6f3 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -258,6 +258,12 @@ dldo7 {
};
};
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_cfg>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index 4eef81d583f3d..e922e05ff856d 100644
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -73,6 +73,27 @@ i2c8-0-pins {
};
};
+ qspi_cfg: qspi-cfg {
+ qspi-pins {
+ pinmux = <K1_PADCONF(98, 0)>, /* QSPI_DATA3 */
+ <K1_PADCONF(99, 0)>, /* QSPI_DATA2 */
+ <K1_PADCONF(100, 0)>, /* QSPI_DATA1 */
+ <K1_PADCONF(101, 0)>, /* QSPI_DATA0 */
+ <K1_PADCONF(102, 0)>; /* QSPI_CLK */
+
+ bias-disable;
+ drive-strength = <19>;
+ power-source = <3300>;
+ };
+
+ qspi-cs1-pins {
+ pinmux = <K1_PADCONF(103, 0)>; /* QSPI_CS1 */
+ bias-pull-up = <0>;
+ drive-strength = <19>;
+ power-source = <3300>;
+ };
+ };
+
/omit-if-no-ref/
uart0_0_cfg: uart0-0-cfg {
uart0-0-pins {
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index af35f9cd64351..47f97105bff0b 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -823,6 +823,22 @@ uart9: serial@...17800 {
status = "disabled";
};
+ qspi: spi@...0c000 {
+ compatible = "spacemit,k1-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xd420c000 0x0 0x1000>,
+ <0x0 0xb8000000 0x0 0xc00000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ clocks = <&syscon_apmu CLK_QSPI_BUS>,
+ <&syscon_apmu CLK_QSPI>;
+ clock-names = "qspi_en", "qspi";
+ resets = <&syscon_apmu RESET_QSPI>,
+ <&syscon_apmu RESET_QSPI_BUS>;
+ interrupts = <117>;
+ status = "disabled";
+ };
+
/* sec_uart1: 0xf0612000, not available from Linux */
};
--
2.48.1
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