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Message-ID: <eed15c43-dde3-410b-b2a3-655f4acf8d97@tuxon.dev>
Date: Mon, 20 Oct 2025 22:15:30 +0300
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, mturquette@...libre.com, sboyd@...nel.org,
alexandre.belloni@...tlin.com, nicolas.ferre@...rochip.com
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, varshini.rajendran@...rochip.com
Subject: Re: [PATCH v4 21/31] clk: at91: dt-compat: switch to parent_hw and
parent_data
Hi, Ryan,
On 9/19/25 00:16, Ryan.Wanner@...rochip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@...on.dev>
>
> Switch old dt-compat clocks to use parent_hw and parent_data. Having
> parent_hw instead of parent names improves to clock registration
> speed and re-parenting.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...on.dev>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
> ---
> drivers/clk/at91/dt-compat.c | 80 +++++++++++++++++++++++++-----------
> 1 file changed, 56 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c
> index fa8658d3be7b..9ca871b817e0 100644
> --- a/drivers/clk/at91/dt-compat.c
> +++ b/drivers/clk/at91/dt-compat.c
> @@ -43,7 +43,8 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
>
> parent_name = of_clk_get_parent_name(np, 0);
>
> - hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name, NULL);
> + hw = at91_clk_register_audio_pll_frac(regmap, name, NULL,
> + &AT91_CLK_PD_NAME(parent_name));
> if (IS_ERR(hw))
> return;
>
> @@ -69,7 +70,8 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
>
> parent_name = of_clk_get_parent_name(np, 0);
>
> - hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name, NULL);
> + hw = at91_clk_register_audio_pll_pad(regmap, name, NULL,
> + &AT91_CLK_PD_NAME(parent_name));
> if (IS_ERR(hw))
> return;
>
> @@ -95,7 +97,7 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
>
> parent_name = of_clk_get_parent_name(np, 0);
>
> - hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name, NULL);
> + hw = at91_clk_register_audio_pll_pmc(regmap, name, NULL, &AT91_CLK_PD_NAME(parent_name));
> if (IS_ERR(hw))
> return;
>
> @@ -129,6 +131,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
> struct clk_hw *hw;
> unsigned int num_parents;
> const char *parent_names[GENERATED_SOURCE_MAX];
> + struct clk_parent_data parent_data[GENERATED_SOURCE_MAX];
> struct device_node *gcknp, *parent_np;
> struct clk_range range = CLK_RANGE(0, 0);
> struct regmap *regmap;
> @@ -149,6 +152,8 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
> if (IS_ERR(regmap))
> return;
>
> + for (unsigned int i = 0; i < num_parents; i++)
> + parent_data[i] = AT91_CLK_PD_NAME(parent_names[i]);
> for_each_child_of_node(np, gcknp) {
> int chg_pid = INT_MIN;
>
> @@ -171,7 +176,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
>
> hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
> &dt_pcr_layout, name,
> - parent_names, NULL, NULL,
> + NULL, parent_data, NULL,
> num_parents, id, &range,
> chg_pid);
> if (IS_ERR(hw))
> @@ -201,7 +206,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
>
> parent_name = of_clk_get_parent_name(np, 0);
>
> - hw = at91_clk_register_h32mx(regmap, name, parent_name, NULL);
> + hw = at91_clk_register_h32mx(regmap, name, NULL, &AT91_CLK_PD_NAME(parent_name));
> if (IS_ERR(hw))
> return;
>
> @@ -228,6 +233,8 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
> return;
>
> for_each_child_of_node(np, i2s_mux_np) {
> + struct clk_parent_data parent_data[2];
> +
> if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
> continue;
>
> @@ -238,8 +245,10 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
> if (ret != 2)
> continue;
>
> + parent_data[0] = AT91_CLK_PD_NAME(parent_names[0]);
> + parent_data[1] = AT91_CLK_PD_NAME(parent_names[1]);
> hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
> - parent_names, NULL, 2, bus_id);
> + NULL, parent_data, 2, bus_id);
> if (IS_ERR(hw))
> continue;
>
> @@ -269,7 +278,8 @@ static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
> if (IS_ERR(regmap))
> return;
>
> - hw = at91_clk_register_main_osc(regmap, name, parent_name, NULL, bypass);
> + hw = at91_clk_register_main_osc(regmap, name, NULL,
> + &AT91_CLK_PD_NAME(parent_name), bypass);
> if (IS_ERR(hw))
> return;
>
> @@ -323,7 +333,7 @@ static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
> if (IS_ERR(regmap))
> return;
>
> - hw = at91_clk_register_rm9200_main(regmap, name, parent_name, NULL);
> + hw = at91_clk_register_rm9200_main(regmap, name, NULL, &AT91_CLK_PD_NAME(parent_name));
> if (IS_ERR(hw))
> return;
>
> @@ -336,6 +346,7 @@ static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
> {
> struct clk_hw *hw;
> const char *parent_names[2];
> + struct clk_parent_data parent_data[2];
> unsigned int num_parents;
> const char *name = np->name;
> struct regmap *regmap;
> @@ -354,7 +365,9 @@ static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
>
> of_property_read_string(np, "clock-output-names", &name);
>
> - hw = at91_clk_register_sam9x5_main(regmap, name, parent_names, NULL,
> + parent_data[0] = AT91_CLK_PD_NAME(parent_names[0]);
> + parent_data[1] = AT91_CLK_PD_NAME(parent_names[1]);
> + hw = at91_clk_register_sam9x5_main(regmap, name, NULL, parent_data,
> num_parents);
> if (IS_ERR(hw))
> return;
> @@ -396,6 +409,7 @@ of_at91_clk_master_setup(struct device_node *np,
> struct clk_hw *hw;
> unsigned int num_parents;
> const char *parent_names[MASTER_SOURCE_MAX];
> + struct clk_parent_data parent_data[MASTER_SOURCE_MAX];
> const char *name = np->name;
> struct clk_master_characteristics *characteristics;
> struct regmap *regmap;
> @@ -419,13 +433,15 @@ of_at91_clk_master_setup(struct device_node *np,
> if (IS_ERR(regmap))
> return;
>
> + for (unsigned int i = 0; i < MASTER_SOURCE_MAX; i++)
> + parent_data[i] = AT91_CLK_PD_NAME(parent_names[i]);
> hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
> - parent_names, NULL, layout,
> + NULL, parent_data, layout,
> characteristics, &mck_lock);
> if (IS_ERR(hw))
> goto out_free_characteristics;
>
> - hw = at91_clk_register_master_div(regmap, name, "masterck_pres", NULL,
> + hw = at91_clk_register_master_div(regmap, name, NULL, &AT91_CLK_PD_HW(hw),
> layout, characteristics,
> &mck_lock, CLK_SET_RATE_GATE, 0);
Looks like at91_clk_register_master_div() could be kept to use parent_hws
instead of parent_data.
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