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Message-ID: <253d329d-12f9-478b-833e-096fafa4b109@tuxon.dev>
Date: Mon, 20 Oct 2025 22:41:23 +0300
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, mturquette@...libre.com, sboyd@...nel.org,
alexandre.belloni@...tlin.com, nicolas.ferre@...rochip.com
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, varshini.rajendran@...rochip.com
Subject: Re: [PATCH v4 04/31] clk: at91: clk-sam9x60-pll: use clk_parent_data
Hi, Ryan,
On 9/19/25 00:15, Ryan.Wanner@...rochip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@...on.dev>
>
> Use struct clk_parent_data instead of struct parent_hw as this leads
> to less usage of __clk_get_hw() in SoC specific clock drivers and simpler
> conversion of existing SoC specific clock drivers from parent_names to
> modern clk_parent_data structures. As clk-sam9x60-pll need to know
> parent's rate at initialization we pass it now from SoC specific drivers.
> This will lead in the end at removing __clk_get_hw() in SoC specific
> drivers (that will be solved by subsequent commits).
>
> Get the main_xtal name via of_clk_get_parent_name() to consistently get
> the correct name for the main_xtal.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...on.dev>
> [ryan.wanner@...rochip.com: Add SAMA7D65 and SAM9X75 SoCs to the change set.]
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++---------
> drivers/clk/at91/pmc.h | 5 +++--
> drivers/clk/at91/sam9x60.c | 8 +++++---
> drivers/clk/at91/sam9x7.c | 16 +++++++++++-----
> drivers/clk/at91/sama7d65.c | 25 ++++++++++++++-----------
> drivers/clk/at91/sama7g5.c | 26 +++++++++++++++-----------
> 6 files changed, 53 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 3dc75a394ce1..9895881c67d7 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = {
>
> struct clk_hw * __init
> sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> - const char *name, const char *parent_name,
> - struct clk_hw *parent_hw, u8 id,
> + const char *name, const struct clk_parent_data *parent_data,
> + unsigned long parent_rate, u8 id,
> const struct clk_pll_characteristics *characteristics,
> const struct clk_pll_layout *layout, u32 flags)
> {
> struct sam9x60_frac *frac;
> struct clk_hw *hw;
> struct clk_init_data init = {};
> - unsigned long parent_rate, irqflags;
> + unsigned long irqflags;
> unsigned int val;
> int ret;
>
> - if (id > PLL_MAX_ID || !lock || !parent_hw)
> + if (id > PLL_MAX_ID || !lock || !parent_data)
> return ERR_PTR(-EINVAL);
>
> frac = kzalloc(sizeof(*frac), GFP_KERNEL);
> @@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> return ERR_PTR(-ENOMEM);
>
> init.name = name;
> - if (parent_name)
> - init.parent_names = &parent_name;
> - else
> - init.parent_hws = (const struct clk_hw **)&parent_hw;
> + init.parent_data = (const struct clk_parent_data *)parent_data;
> init.num_parents = 1;
> if (flags & CLK_SET_RATE_GATE)
> init.ops = &sam9x60_frac_pll_ops;
> @@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> * its rate leading to enabling this PLL with unsupported
> * rate. This will lead to PLL not being locked at all.
> */
> - parent_rate = clk_hw_get_rate(parent_hw);
> if (!parent_rate) {
> hw = ERR_PTR(-EINVAL);
> goto free;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 16c2559889aa..d3fc38cf90eb 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -258,8 +258,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>
> struct clk_hw * __init
> sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> - const char *name, const char *parent_name,
> - struct clk_hw *parent_hw, u8 id,
> + const char *name,
> + const struct clk_parent_data *parent_data,
> + unsigned long parent_rate, u8 id,
> const struct clk_pll_characteristics *characteristics,
> const struct clk_pll_layout *layout, u32 flags);
>
> diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
> index 18baf4a256f4..bee35c65aceb 100644
> --- a/drivers/clk/at91/sam9x60.c
> +++ b/drivers/clk/at91/sam9x60.c
> @@ -242,7 +242,8 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
> sam9x60_pmc->chws[PMC_MAIN] = hw;
>
> hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
> - "mainck", sam9x60_pmc->chws[PMC_MAIN],
> + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]),
> + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]),
> 0, &plla_characteristics,
> &pll_frac_layout,
> /*
> @@ -268,8 +269,9 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
> sam9x60_pmc->chws[PMC_PLLACK] = hw;
>
> hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
> - "main_osc", main_osc_hw, 1,
> - &upll_characteristics,
> + &AT91_CLK_PD_HW(main_osc_hw),
> + clk_hw_get_rate(main_osc_hw),
> + 1, &upll_characteristics,
> &pll_frac_layout, CLK_SET_RATE_GATE);
> if (IS_ERR(hw))
> goto err_free;
> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
> index cb5849da494f..c80306715d90 100644
> --- a/drivers/clk/at91/sam9x7.c
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -752,6 +752,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
> struct regmap *regmap;
> struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
> struct clk_hw *td_slck_hw, *md_slck_hw, *usbck_hw;
> + static struct clk_parent_data parent_data;
> struct clk_hw *parent_hws[9];
> int i, j;
>
> @@ -799,7 +800,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
>
> for (i = 0; i < PLL_ID_MAX; i++) {
> for (j = 0; j < PLL_COMPID_MAX; j++) {
> - struct clk_hw *parent_hw;
> + unsigned long parent_rate;
>
> if (!sam9x7_plls[i][j].n)
> continue;
> @@ -808,21 +809,26 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
> case PLL_TYPE_FRAC:
> switch (sam9x7_plls[i][j].p) {
> case SAM9X7_PLL_PARENT_MAINCK:
> - parent_hw = sam9x7_pmc->chws[PMC_MAIN];
> + parent_data = AT91_CLK_PD_NAME("mainck");
> + hw = sam9x7_pmc->chws[PMC_MAIN];
> break;
> case SAM9X7_PLL_PARENT_MAIN_XTAL:
> - parent_hw = main_xtal_hw;
> + parent_data = AT91_CLK_PD_NAME(main_xtal_name);
> + hw = main_xtal_hw;
> break;
> default:
> /* Should not happen. */
> - parent_hw = NULL;
> break;
> }
>
> + parent_rate = clk_hw_get_rate(hw);
> + if (!parent_rate)
> + return;
> +
> hw = sam9x60_clk_register_frac_pll(regmap,
> &pmc_pll_lock,
> sam9x7_plls[i][j].n,
> - NULL, parent_hw, i,
> + &parent_data, parent_rate, i,
> sam9x7_plls[i][j].c,
> sam9x7_plls[i][j].l,
> sam9x7_plls[i][j].f);
> diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
> index ec2ef1a0249a..6229b7dfbea1 100644
> --- a/drivers/clk/at91/sama7d65.c
> +++ b/drivers/clk/at91/sama7d65.c
> @@ -1093,7 +1093,7 @@ static const struct clk_pcr_layout sama7d65_pcr_layout = {
>
> static void __init sama7d65_pmc_setup(struct device_node *np)
> {
> - const char *main_xtal_name = "main_xtal";
> + const char *main_xtal_name;
> struct pmc_data *sama7d65_pmc;
> const char *parent_names[11];
> void **alloc_mem = NULL;
> @@ -1108,10 +1108,11 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
>
> td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck"));
> md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck"));
> - main_xtal_hw = __clk_get_hw(of_clk_get_by_name(np, main_xtal_name));
> + i = of_property_match_string(np, "clock-names", "main_xtal");
Same as in the previous patch, please keep it close to
of_clk_get_parent_name() for main_xtal above and check check also negative
error numbers return by of_property_match_string(). Valid for the other
similar occurrences in this or next patches.
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