linux-kernel - Re: [PATCH v4 06/31] clk: at91: clk-main: switch to clk parent data

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Message-ID: <e5f4a505-86ff-4d89-86d6-5433cf7c5665@tuxon.dev>
Date: Mon, 20 Oct 2025 22:42:43 +0300
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, mturquette@...libre.com, sboyd@...nel.org,
 alexandre.belloni@...tlin.com, nicolas.ferre@...rochip.com
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, varshini.rajendran@...rochip.com
Subject: Re: [PATCH v4 06/31] clk: at91: clk-main: switch to clk parent data

Hi, Ryan,

On 9/19/25 00:15, Ryan.Wanner@...rochip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@...on.dev>
> 
> Use struct clk_parent_data instead of parent_hw for the main clock
> to less usage of __clk_get_hw() in SoC specific clock drivers and simpler

Probably missing "This" in front of "to less" or something similar?

> conversion of existing SoC specific clock drivers from parent_names to
> modern clk_parent_data structures. This will lead in the end at removing
> __clk_get_hw() in SoC specific drivers
> (that will be solved by subsequent commits).
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...on.dev>
> [ryan.wanner@...rochip: Add SAMA7D65 and SAM9X75 SoCs to use parent_data.]
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
> ---


[...]

> @@ -1020,9 +1020,9 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
>  	if (IS_ERR(main_osc_hw))
>  		goto err_free;
>  
> -	parent_hws[0] = main_rc_hw;
> -	parent_hws[1] = main_osc_hw;
> -	hw = at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, 2);
> +	parent_data[0] = AT91_CLK_PD_HW(main_rc_hw);
> +	parent_data[1] = AT91_CLK_PD_HW(main_osc_hw);

You missed to convert parent data to an array and adjust use it accordingly
in this file.

> +	hw = at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data, 2);
>  	if (IS_ERR(hw))
>  		goto err_free;
>  
> @@ -1057,7 +1057,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
>  
>  				hw = sam9x60_clk_register_frac_pll(regmap,
>  					&pmc_pll_lock, sama7g5_plls[i][j].n,
> -					&parent_data, parent_rate, i,
> +					parent_data, parent_rate, i,
>  					sama7g5_plls[i][j].c,
>  					sama7g5_plls[i][j].l,
>  					sama7g5_plls[i][j].f);