| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20251020211740.719676-6-benato.denis96@gmail.com>
Date: Mon, 20 Oct 2025 23:17:36 +0200
From: Denis Benato <benato.denis96@...il.com>
To: linux-kernel@...r.kernel.org
Cc: platform-driver-x86@...r.kernel.org,
"Hans de Goede" <hdegoede@...hat.com>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
"Limonciello, Mario" <mario.limonciello@....com>,
"Luke D . Jones" <luke@...nes.dev>,
"Alok Tiwari" <alok.a.tiwari@...cle.com>,
"Derek John Clark" <derekjohn.clark@...il.com>,
"Mateusz Schyboll" <dragonn@...pl>,
porfet828@...il.com,
Denis Benato <benato.denis96@...il.com>
Subject: [PATCH v15 5/9] platform/x86: asus-armoury: add core count control
From: "Luke D. Jones" <luke@...nes.dev>
Implement Intel core enablement under the asus-armoury module using the
fw_attributes class.
This allows users to enable or disable preformance or efficiency cores
depending on their requirements. After change a reboot is required.
Signed-off-by: Denis Benato <benato.denis96@...il.com>
Signed-off-by: Luke D. Jones <luke@...nes.dev>
---
drivers/platform/x86/asus-armoury.c | 284 +++++++++++++++++++++
drivers/platform/x86/asus-armoury.h | 28 ++
include/linux/platform_data/x86/asus-wmi.h | 5 +
3 files changed, 317 insertions(+)
diff --git a/drivers/platform/x86/asus-armoury.c b/drivers/platform/x86/asus-armoury.c
index fe80d5d04300..1b34c929a0b4 100644
--- a/drivers/platform/x86/asus-armoury.c
+++ b/drivers/platform/x86/asus-armoury.c
@@ -48,6 +48,36 @@
#define ASUS_MINI_LED_2024_STRONG 0x01
#define ASUS_MINI_LED_2024_OFF 0x02
+#define ASUS_POWER_CORE_MASK GENMASK(15, 8)
+#define ASUS_PERF_CORE_MASK GENMASK(7, 0)
+
+enum cpu_core_type {
+ CPU_CORE_PERF = 0,
+ CPU_CORE_POWER,
+};
+
+enum cpu_core_value {
+ CPU_CORE_DEFAULT = 0,
+ CPU_CORE_MIN,
+ CPU_CORE_MAX,
+ CPU_CORE_CURRENT,
+};
+
+/* Minimum number of performance cores (P-cores) */
+#define CPU_PERF_CORE_COUNT_MIN 4
+/* Minimum number of efficiency cores (E-cores) */
+#define CPU_POWR_CORE_COUNT_MIN 0
+
+/* Tunables provided by ASUS for gaming laptops */
+struct cpu_cores {
+ u32 cur_perf_cores;
+ u32 min_perf_cores;
+ u32 max_perf_cores;
+ u32 cur_power_cores;
+ u32 min_power_cores;
+ u32 max_power_cores;
+};
+
struct asus_armoury_priv {
struct device *fw_attr_dev;
struct kset *fw_attr_kset;
@@ -60,12 +90,22 @@ struct asus_armoury_priv {
*/
struct mutex egpu_mutex;
+ /*
+ * Mutex to prevent big/little core count changes writing to same
+ * endpoint at the same time. Must lock during attr store.
+ */
+ struct mutex cpu_core_mutex;
+ struct cpu_cores *cpu_cores;
+ bool cpu_cores_changeable;
+
u32 mini_led_dev_id;
u32 gpu_mux_dev_id;
};
static struct asus_armoury_priv asus_armoury = {
.egpu_mutex = __MUTEX_INITIALIZER(asus_armoury.egpu_mutex),
+
+ .cpu_core_mutex = __MUTEX_INITIALIZER(asus_armoury.cpu_core_mutex),
};
struct fw_attrs_group {
@@ -97,6 +137,8 @@ static struct kobj_attribute pending_reboot = __ATTR_RO(pending_reboot);
static bool asus_bios_requires_reboot(struct kobj_attribute *attr)
{
return !strcmp(attr->attr.name, "gpu_mux_mode") ||
+ !strcmp(attr->attr.name, "cores_performance") ||
+ !strcmp(attr->attr.name, "cores_efficiency") ||
!strcmp(attr->attr.name, "panel_hd_mode");
}
@@ -199,6 +241,18 @@ static int armoury_set_devstate(struct kobj_attribute *attr,
return -EINVAL;
}
break;
+ case ASUS_WMI_DEVID_CORES:
+ /*
+ * Prevent risk disabling cores essential for booting the system
+ * up to a point where system settings can be reset:
+ * this has already caused unrecoverable bricks in the past.
+ */
+ if ((FIELD_GET(ASUS_POWER_CORE_MASK, value) < CPU_POWR_CORE_COUNT_MIN) ||
+ (FIELD_GET(ASUS_PERF_CORE_MASK, value) < CPU_PERF_CORE_COUNT_MIN)) {
+ pr_err("Refusing to set CPU cores to unsafe value: 0x%x\n", value);
+ return -EINVAL;
+ }
+ break;
default:
/* No known problems are known for this dev_id */
break;
@@ -297,6 +351,12 @@ static ssize_t enum_type_show(struct kobject *kobj, struct kobj_attribute *attr,
return sysfs_emit(buf, "enumeration\n");
}
+static ssize_t int_type_show(struct kobject *kobj, struct kobj_attribute *attr,
+ char *buf)
+{
+ return sysfs_emit(buf, "integer\n");
+}
+
/* Mini-LED mode **************************************************************/
static ssize_t mini_led_mode_current_value_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
@@ -690,6 +750,213 @@ static ssize_t apu_mem_possible_values_show(struct kobject *kobj, struct kobj_at
}
ASUS_ATTR_GROUP_ENUM(apu_mem, "apu_mem", "Set available system RAM (in GB) for the APU to use");
+static struct cpu_cores *init_cpu_cores_ctrl(void)
+{
+ u32 cores;
+ int err;
+ struct cpu_cores *cores_p __free(kfree) = NULL;
+
+ cores_p = kzalloc(sizeof(struct cpu_cores), GFP_KERNEL);
+ if (!cores_p)
+ return ERR_PTR(-ENOMEM);
+
+ err = armoury_get_devstate(NULL, &cores, ASUS_WMI_DEVID_CORES_MAX);
+ if (err) {
+ pr_err("ACPI does not support CPU core count control\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ cores_p->max_power_cores = FIELD_GET(ASUS_POWER_CORE_MASK, cores);
+ cores_p->max_perf_cores = FIELD_GET(ASUS_PERF_CORE_MASK, cores);
+
+ err = armoury_get_devstate(NULL, &cores, ASUS_WMI_DEVID_CORES);
+ if (err) {
+ pr_err("Could not get CPU core count: error %d\n", err);
+ return ERR_PTR(-EIO);
+ }
+
+ cores_p->cur_power_cores = FIELD_GET(ASUS_POWER_CORE_MASK, cores);
+ cores_p->cur_perf_cores = FIELD_GET(ASUS_PERF_CORE_MASK, cores);
+
+ cores_p->min_power_cores = CPU_POWR_CORE_COUNT_MIN;
+ cores_p->min_perf_cores = CPU_PERF_CORE_COUNT_MIN;
+
+ if ((cores_p->min_perf_cores > cores_p->max_perf_cores) ||
+ (cores_p->min_power_cores > cores_p->max_power_cores) ||
+ (cores_p->cur_perf_cores > cores_p->max_perf_cores) ||
+ (cores_p->cur_power_cores > cores_p->max_power_cores) ||
+ (cores_p->cur_perf_cores < cores_p->min_perf_cores) ||
+ (cores_p->cur_power_cores < cores_p->min_power_cores)
+ ) {
+ pr_err("Invalid CPU cores count detected: interface is not safe to be used.\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return no_free_ptr(cores_p);
+}
+
+static ssize_t cores_value_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf,
+ enum cpu_core_type core_type, enum cpu_core_value core_value)
+{
+ u32 cpu_core_value;
+
+ switch (core_value) {
+ case CPU_CORE_DEFAULT:
+ case CPU_CORE_MAX:
+ cpu_core_value = (core_type == CPU_CORE_PERF) ?
+ asus_armoury.cpu_cores->max_perf_cores :
+ asus_armoury.cpu_cores->max_power_cores;
+ break;
+ case CPU_CORE_MIN:
+ cpu_core_value = (core_type == CPU_CORE_PERF) ?
+ asus_armoury.cpu_cores->min_perf_cores :
+ asus_armoury.cpu_cores->min_power_cores;
+ break;
+ case CPU_CORE_CURRENT:
+ cpu_core_value = (core_type == CPU_CORE_PERF) ?
+ asus_armoury.cpu_cores->cur_perf_cores :
+ asus_armoury.cpu_cores->cur_power_cores;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return sysfs_emit(buf, "%u\n", cpu_core_value);
+}
+
+static ssize_t cores_current_value_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, enum cpu_core_type core_type)
+{
+ u32 new_cores, perf_cores, power_cores, out_val, min, max, result;
+ int err;
+
+ result = kstrtou32(buf, 10, &new_cores);
+ if (result)
+ return result;
+
+ scoped_guard(mutex, &asus_armoury.cpu_core_mutex) {
+ if (!asus_armoury.cpu_cores_changeable) {
+ pr_warn("CPU core count change not allowed until reboot\n");
+ return -EBUSY;
+ }
+
+ if (core_type == CPU_CORE_PERF) {
+ perf_cores = new_cores;
+ power_cores = asus_armoury.cpu_cores->cur_power_cores;
+ min = asus_armoury.cpu_cores->min_perf_cores;
+ max = asus_armoury.cpu_cores->max_perf_cores;
+ } else {
+ perf_cores = asus_armoury.cpu_cores->cur_perf_cores;
+ power_cores = new_cores;
+ min = asus_armoury.cpu_cores->min_power_cores;
+ max = asus_armoury.cpu_cores->max_power_cores;
+ }
+
+ if (new_cores < min || new_cores > max)
+ return -EINVAL;
+
+ out_val = FIELD_PREP(ASUS_PERF_CORE_MASK, perf_cores) |
+ FIELD_PREP(ASUS_POWER_CORE_MASK, power_cores);
+
+ asus_armoury.cpu_cores_changeable = false;
+ err = armoury_set_devstate(attr, out_val, &result, ASUS_WMI_DEVID_CORES);
+ if (err) {
+ pr_warn("Failed to set CPU core count: %d\n", err);
+ return err;
+ }
+
+ if (result > 1) {
+ pr_warn("Failed to set CPU core count (result): 0x%x\n", result);
+ return -EIO;
+ }
+ }
+
+ pr_info("CPU core count changed, reboot required\n");
+
+ sysfs_notify(kobj, NULL, attr->attr.name);
+ asus_set_reboot_and_signal_event();
+
+ return 0;
+}
+
+static ssize_t cores_performance_min_value_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_PERF, CPU_CORE_MIN);
+}
+
+static ssize_t cores_performance_max_value_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_PERF, CPU_CORE_MAX);
+}
+
+static ssize_t cores_performance_default_value_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_PERF, CPU_CORE_DEFAULT);
+}
+
+static ssize_t cores_performance_current_value_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_PERF, CPU_CORE_CURRENT);
+}
+
+static ssize_t cores_performance_current_value_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ int err;
+
+ err = cores_current_value_store(kobj, attr, buf, CPU_CORE_PERF);
+ if (err)
+ return err;
+
+ return count;
+}
+ASUS_ATTR_GROUP_CORES_RW(cores_performance, "cores_performance",
+ "Set the max available performance cores");
+
+static ssize_t cores_efficiency_min_value_show(struct kobject *kobj, struct kobj_attribute *attr,
+ char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_POWER, CPU_CORE_MIN);
+}
+
+static ssize_t cores_efficiency_max_value_show(struct kobject *kobj, struct kobj_attribute *attr,
+ char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_POWER, CPU_CORE_MAX);
+}
+
+static ssize_t cores_efficiency_default_value_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_POWER, CPU_CORE_DEFAULT);
+}
+
+static ssize_t cores_efficiency_current_value_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return cores_value_show(kobj, attr, buf, CPU_CORE_POWER, CPU_CORE_CURRENT);
+}
+
+static ssize_t cores_efficiency_current_value_store(struct kobject *kobj,
+ struct kobj_attribute *attr, const char *buf,
+ size_t count)
+{
+ int err;
+
+ err = cores_current_value_store(kobj, attr, buf, CPU_CORE_POWER);
+ if (err)
+ return err;
+
+ return count;
+}
+ASUS_ATTR_GROUP_CORES_RW(cores_efficiency, "cores_efficiency",
+ "Set the max available efficiency cores");
+
/* Simple attribute creation */
ASUS_ATTR_GROUP_ENUM_INT_RO(charge_mode, "charge_mode", ASUS_WMI_DEVID_CHARGE_MODE, "0;1;2",
"Show the current mode of charging");
@@ -710,6 +977,8 @@ static const struct asus_attr_group armoury_attr_groups[] = {
{ &egpu_enable_attr_group, ASUS_WMI_DEVID_EGPU },
{ &dgpu_disable_attr_group, ASUS_WMI_DEVID_DGPU },
{ &apu_mem_attr_group, ASUS_WMI_DEVID_APU_MEM },
+ { &cores_efficiency_attr_group, ASUS_WMI_DEVID_CORES_MAX },
+ { &cores_performance_attr_group, ASUS_WMI_DEVID_CORES_MAX },
{ &charge_mode_attr_group, ASUS_WMI_DEVID_CHARGE_MODE },
{ &boot_sound_attr_group, ASUS_WMI_DEVID_BOOT_SOUND },
@@ -813,6 +1082,8 @@ static int asus_fw_attr_add(void)
static int __init asus_fw_init(void)
{
char *wmi_uid;
+ struct cpu_cores *cpu_cores_ctrl;
+ int err;
wmi_uid = wmi_get_acpi_device_uid(ASUS_WMI_MGMT_GUID);
if (!wmi_uid)
@@ -825,6 +1096,19 @@ static int __init asus_fw_init(void)
if (!strcmp(wmi_uid, ASUS_ACPI_UID_ASUSWMI))
return -ENODEV;
+ asus_armoury.cpu_cores_changeable = false;
+ if (armoury_has_devstate(ASUS_WMI_DEVID_CORES_MAX)) {
+ cpu_cores_ctrl = init_cpu_cores_ctrl();
+ if (IS_ERR(cpu_cores_ctrl)) {
+ err = PTR_ERR(cpu_cores_ctrl);
+ pr_err("Could not initialise CPU core control: %d\n", err);
+ return err;
+ }
+
+ asus_armoury.cpu_cores = cpu_cores_ctrl;
+ asus_armoury.cpu_cores_changeable = true;
+ }
+
return asus_fw_attr_add();
}
diff --git a/drivers/platform/x86/asus-armoury.h b/drivers/platform/x86/asus-armoury.h
index 9f2c98df5fd7..c9f89f873251 100644
--- a/drivers/platform/x86/asus-armoury.h
+++ b/drivers/platform/x86/asus-armoury.h
@@ -160,4 +160,32 @@
.name = _fsname, .attrs = _attrname##_attrs \
}
+/* CPU core attributes need a little different in setup */
+#define ASUS_ATTR_GROUP_CORES_RW(_attrname, _fsname, _dispname) \
+ __ATTR_SHOW_FMT(scalar_increment, _attrname, "%d\n", 1); \
+ __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \
+ static struct kobj_attribute attr_##_attrname##_current_value = \
+ __ASUS_ATTR_RW(_attrname, current_value); \
+ static struct kobj_attribute attr_##_attrname##_default_value = \
+ __ASUS_ATTR_RO(_attrname, default_value); \
+ static struct kobj_attribute attr_##_attrname##_min_value = \
+ __ASUS_ATTR_RO(_attrname, min_value); \
+ static struct kobj_attribute attr_##_attrname##_max_value = \
+ __ASUS_ATTR_RO(_attrname, max_value); \
+ static struct kobj_attribute attr_##_attrname##_type = \
+ __ASUS_ATTR_RO_AS(type, int_type_show); \
+ static struct attribute *_attrname##_attrs[] = { \
+ &attr_##_attrname##_current_value.attr, \
+ &attr_##_attrname##_default_value.attr, \
+ &attr_##_attrname##_min_value.attr, \
+ &attr_##_attrname##_max_value.attr, \
+ &attr_##_attrname##_scalar_increment.attr, \
+ &attr_##_attrname##_display_name.attr, \
+ &attr_##_attrname##_type.attr, \
+ NULL \
+ }; \
+ static const struct attribute_group _attrname##_attr_group = { \
+ .name = _fsname, .attrs = _attrname##_attrs \
+ }
+
#endif /* _ASUS_ARMOURY_H_ */
diff --git a/include/linux/platform_data/x86/asus-wmi.h b/include/linux/platform_data/x86/asus-wmi.h
index a4f6bab93a6f..9a79dae97adf 100644
--- a/include/linux/platform_data/x86/asus-wmi.h
+++ b/include/linux/platform_data/x86/asus-wmi.h
@@ -137,6 +137,11 @@
/* dgpu on/off */
#define ASUS_WMI_DEVID_DGPU 0x00090020
+/* Intel E-core and P-core configuration in a format 0x0[E]0[P] */
+#define ASUS_WMI_DEVID_CORES 0x001200D2
+ /* Maximum Intel E-core and P-core availability */
+#define ASUS_WMI_DEVID_CORES_MAX 0x001200D3
+
#define ASUS_WMI_DEVID_APU_MEM 0x000600C1
/* gpu mux switch, 0 = dGPU, 1 = Optimus */
--
2.51.1
Powered by blists - more mailing lists