linux-kernel - Re: [PATCH v8 07/20] mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction

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Message-ID: <336e7154-b618-466c-a9b5-cc15f0f62a27@collabora.com>
Date: Mon, 20 Oct 2025 12:04:36 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Jason-JH Lin <jason-jh.lin@...iatek.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Jassi Brar <jassisinghbrar@...il.com>,
 Chun-Kuang Hu <chunkuang.hu@...nel.org>,
 Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
 Nicolas Dufresne <nicolas@...fresne.ca>, Nancy Lin <nancy.lin@...iatek.com>,
 Singo Chang <singo.chang@...iatek.com>,
 Paul-PL Chen <paul-pl.chen@...iatek.com>, Moudy Ho <moudy.ho@...iatek.com>,
 Xiandong Wang <xiandong.wang@...iatek.com>,
 Sirius Wang <sirius.wang@...iatek.com>, Fei Shao <fshao@...omium.org>,
 Chen-yu Tsai <wenst@...omium.org>,
 Project_Global_Chrome_Upstream_Group@...iatek.com,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 dri-devel@...ts.freedesktop.org, linux-mediatek@...ts.infradead.org,
 linux-arm-kernel@...ts.infradead.org, linux-media@...r.kernel.org
Subject: Re: [PATCH v8 07/20] mailbox: mtk-cmdq: Add mminfra_offset
 configuration for DRAM transaction

Il 17/10/25 08:44, Jason-JH Lin ha scritto:
> The GCE in MT8196 is placed in MMINFRA and requires all addresses
> in GCE instructions for DRAM transactions to be IOVA.
> 
> Due to MMIO, if the GCE needs to access a hardware register at
> 0x1000_0000, but the SMMU is also mapping a DRAM block at 0x1000_0000,
> the MMINFRA will not know whether to write to the hardware register or
> the DRAM.
> To solve this, MMINFRA treats addresses greater than 2G as data paths
> and those less than 2G as config paths because the DRAM start address
> is currently at 2G (0x8000_0000). On the data path, MMINFRA remaps
> DRAM addresses by subtracting 2G, allowing SMMU to map DRAM addresses
> less than 2G.
> For example, if the DRAM start address 0x8000_0000 is mapped to
> IOVA=0x0, when GCE accesses IOVA=0x0, it must add a 2G offset to
> the address in the GCE instruction. MMINFRA will then see it as a
> data path (IOVA >= 2G) and subtract 2G, allowing GCE to access IOVA=0x0.
> 
> Since the MMINFRA remap subtracting 2G is done in hardware and cannot
> be configured by software, the address of DRAM in GCE instruction must
> always add 2G to ensure proper access. After that, the shift functions
> do more than just shift addresses, so the APIs were renamed to
> cmdq_convert_gce_addr() and cmdq_revert_gce_addr().
> 
> This 2G adjustment is referred to as mminfra_offset in the CMDQ driver.
> CMDQ helper can get the mminfra_offset from the cmdq_mbox_priv of
> cmdq_pkt and add the mminfra_offset to the DRAM address in GCE
> instructions.
> 
> Signed-off-by: Jason-JH Lin <jason-jh.lin@...iatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>