linux-kernel - Re: [PATCH v1 1/2] cxl_test: enable zero sized decoders under hb0

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Message-ID: <aPeSqjqU6BH9gvcw@gourry-fedora-PF4VCD3F>
Date: Tue, 21 Oct 2025 10:03:22 -0400
From: Gregory Price <gourry@...rry.net>
To: Alison Schofield <alison.schofield@...el.com>
Cc: Vishal Aslot <vaslot@...dia.com>, Davidlohr Bueso <dave@...olabs.net>,
	Jonathan Cameron <jonathan.cameron@...wei.com>,
	Dave Jiang <dave.jiang@...el.com>,
	Vishal Verma <vishal.l.verma@...el.com>,
	Ira Weiny <ira.weiny@...el.com>,
	Dan Williams <dan.j.williams@...el.com>,
	Li Ming <ming.li@...omail.com>,
	Peter Zijlstra <peterz@...radead.org>,
	"open list:COMPUTE EXPRESS LINK (CXL)" <linux-cxl@...r.kernel.org>,
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 1/2] cxl_test: enable zero sized decoders under hb0

On Mon, Oct 20, 2025 at 12:30:21PM -0700, Alison Schofield wrote:
> On Mon, Oct 20, 2025 at 10:19:09AM -0400, Gregory Price wrote:
> > On Mon, Oct 20, 2025 at 12:09:34AM -0700, Alison Schofield wrote:
> > > > This patch updates cxl_test to enable decoders 1 and 2
> > > > in the host-bridge 0 port, in a switch uport under hb0,
> > > > and the endpoints ports with size zero simulating
> > > > committed zero sized decoders.
> > > 
> > > Decoders 1 & 2 - those are after decoder 0, the autoregion.
> > > That's a problem ATM, when we try to teardown the autoregion we
> > > get out of order resets. Like I asked in the other patch, if there
> > > are rules about where these zero size decoders may appear, that
> > > may make the solution here simpler.
> > > 
> > 
> > I think this is going to require a quirk-doc like other deviations.
> 
> Really need to hear more about spec here. You mention quirk, but is it
> really a quirk or spec defined behavior?
>

Quoted below.  Small bit of ambiguity around base=[X] when size=0.

There's no requirement on base for a size=0 decoder, so it sort of implies
the base is ignored - except that the normal commit requires (base+size)
checks on decoder[m]/[m+1] without discussing size=0 decoders.

So while the spec doesn't say the base in a 0-size decoder base address
must be set, if you implement the logic here trivially you will always
fail if the zero-size decoder.base=0.

Note that 14.13.9 also doesn't say firmware must enforce commit-order,
so deviant software could go off and commit decoders out of order.

All the spec says is "If software intends to set Lock On Commit,
Software must configure the decoders in order".

~Gregory

------------------------------------------

Re commit order - Vishal said they do post-lock order
https://lore.kernel.org/linux-cxl/aOP3Kr3jHLWOydRp@gourry-fedora-PF4VCD3F/

Post-lock order
[programmable] [zero-lock] [zero-lock] ... [zero-lock]

Pre-lock order:
[zero-lock] [zero-lock] ... [zero-lock] [programmable]

My reading of the spec suggests that Post-lock ordering is *not legal*,
and would suggest the software has deviated from the spec - which does
not allow for size-zero decoders to ignore commit order.

------------------------------------------
8.2.4.20.12: Committing Decoder Programming

If Software intends to set Lock On Commit, Software must configure the
decoders in order. In other words, decoder m must be configured and
committed before decoder m+1 for all values of m.

Decoder m must cover an HPA range that is below decoder m+1.

...

It is legal for software to program Decoder Size to 0 and commit it. Such a decoder will
not participate in HDM decode.

------------------------------------------
14.13.10: CXL HDM Decoder Zero Size Commit

Test Steps:
  1. Program 0 in the Decoder[m].Size register.
  2. Set the Commit bit in the Decoder[m].Control register.

Pass Criteria:
  • Committed bit in the Decoder[m].Control register is set
  • Error Not Committed bit in the Decoder[].Control register is not set

Fail Conditions:
  • Committed bit in the Decoder[m].Control register is not set within 10 ms
  • Error Not Committed bit in the Decoder[m].Control register is set

------------------------------------------
14.13.9 CXL HDM Decoder Commit

Test Steps:
  1. Program an address range in the Decoder[m+1].Base and Decoder[m+1].Size
     registers such that:

     — Decoder[m+1].Base >= (Decoder[m].Base+Decoder[m].Size), and
     — Decoder[m+1].Base <= Decoder[m+1].Base+Decoder[m+1].Size