linux-kernel - Re: [PATCH] irqchip/gicv3-its: Clear cache with VINVALL for erratum 162100801

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Message-ID: <86cy6gwcu3.wl-maz@kernel.org>
Date: Tue, 21 Oct 2025 15:26:12 +0100
From: Marc Zyngier <maz@...nel.org>
To: Jinqian Yang <yangjinqian1@...wei.com>
Cc: <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>,
	<catalin.marinas@....com>,
	<will@...nel.org>,
	<yuzenghui@...wei.com>,
	<wangzhou1@...ilicon.com>,
	<jiangkunkun@...wei.com>,
	<tangnianyao@...wei.com>,
	<wangwudi@...ilicon.com>,
	<liuyonglong@...wei.com>
Subject: Re: [PATCH] irqchip/gicv3-its: Clear cache with VINVALL for erratum 162100801

On Tue, 21 Oct 2025 14:24:01 +0100,
Jinqian Yang <yangjinqian1@...wei.com> wrote:
> 
> Use VINVALL to clear cache after VMOVP operation to avoid incomplete
> cache cleanup. The previous implementation only cleared cache on one
> ITS. This change sends VINVALL to every ITS to properly clear caches.

This isn't the same thing. Why is that a better option? Also, VINVALL
is broadcast to the RDs. Why does it need to be sent to each and every
ITS? If GICR_INVALL, does GICR_INVLPIR work? Does anything work at all
on this implementation?

I'm getting very tired of this constant churn on all of your GIC
implementations that are totally unable to correctly deliver vLPIs and
vSGIs without either a deadlock or some corruption. At this stage, you
should simply disable GICv4 on your HW and stick top something that
actually works.

This should give you the time to build HW that actually works.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.