linux-kernel - Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms

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Message-ID: <20251021153642.GA1190961@bhelgaas>
Date: Tue, 21 Oct 2025 10:36:42 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Manivannan Sadhasivam <mani@...nel.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>,
	Christian Zigotzky <chzigotzky@...osoft.de>,
	FUKAUMI Naoki <naoki@...xa.com>, linux-rockchip@...r.kernel.org,
	linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
	Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms

On Tue, Oct 21, 2025 at 09:31:22AM +0530, Manivannan Sadhasivam wrote:
> On Mon, Oct 20, 2025 at 05:12:07PM -0500, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas <bhelgaas@...gle.com>
> > 
> > f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree
> > platforms") enabled Clock Power Management and L1 Substates, but that
> > caused regressions because these features depend on CLKREQ#, and not all
> > devices and form factors support it.
> 
> I believe we haven't concluded that CLKREQ# is the cluprit here. It
> is probably the best bet, but there could be the device specific
> issues as well.

Yes.  There might be things in addition to CLKREQ#, but Clock PM and
L1SS definitely can't work without CLKREQ#.  I'll try to convey that
somehow.

> > Reported-by: Christian Zigotzky <chzigotzky@...osoft.de>
> > Link: https://lore.kernel.org/r/db5c95a1-cf3e-46f9-8045-a1b04908051a@xenosoft.de/
> 
> Closes?

Yes, makes sense.  I didn't use Closes yet because I didn't want to
presume that it actually fixed the issue.  Will change if we get
testing results.

> > +	/* For devicetree platforms, enable L0s and L1 by default */
> >  	if (of_have_populated_dt()) {
> > -		link->aspm_default = PCIE_LINK_STATE_ASPM_ALL;
> > +		if (link->aspm_support & PCIE_LINK_STATE_L0S)
> > +			link->aspm_default |= PCIE_LINK_STATE_L0S;
> > +		if (link->aspm_support & PCIE_LINK_STATE_L1)
> > +			link->aspm_default |= PCIE_LINK_STATE_L1;
> 
> Not sure if it is worth setting these states conditionally. Link
> state enablement code should make use of the cached ASPM cap in
> 'link->aspm_capable'.

I wanted to avoid mentioning an ASPM state that is not advertised in
Link Capabilities, even if later code would ignore it.

> > +			pci_info(pdev, "ASPM: DT platform, enabling%s%s\n",
> 
> I think you added the 'DT platform,' prefix while applying my patch
> earlier.  This is somewhat redundant since the print implies that
> the platform is based on devicetree.

I think "DT platform" is probably unnecessary clutter.  I'll drop it
next time.