| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20251021-dastardly-washbowl-b8c4ec1745db@spud>
Date: Tue, 21 Oct 2025 16:38:37 +0100
From: Conor Dooley <conor@...nel.org>
To: linux-riscv@...ts.infradead.org
Cc: conor@...nel.org,
Conor Dooley <conor.dooley@...rochip.com>,
stable@...r.kernel.org,
Valentina.FernandezAlanis@...rochip.com,
Cyril.Jean@...rochip.com,
Daire McNamara <daire.mcnamara@...rochip.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Jamie Gibbons <jamie.gibbons@...rochip.com>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v1] riscv: dts: microchip: remove BeagleV Fire fabric.dtsi
From: Conor Dooley <conor.dooley@...rochip.com>
At the time of adding the fabric.dtsi for the BeagleV Fire, we thought
that the fabric nodes in the Beagle supplied images were stable. They
are not, which has lead to nodes present in the devicetree that are not
in the programmed FPGA images. This is obviously problematic, and these
nodes must be removed.
CC: stable@...r.kernel.org
Fixes: 3f41368fbfe1 ("riscv: dts: microchip: add an initial devicetree for the BeagleV Fire")
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
--
CC: Valentina.FernandezAlanis@...rochip.com
CC: Cyril.Jean@...rochip.com
CC: Conor Dooley <conor@...nel.org>
CC: Daire McNamara <daire.mcnamara@...rochip.com>
CC: Rob Herring <robh@...nel.org>
CC: Krzysztof Kozlowski <krzk+dt@...nel.org>
CC: Paul Walmsley <paul.walmsley@...ive.com>
CC: Jamie Gibbons <jamie.gibbons@...rochip.com>
CC: linux-riscv@...ts.infradead.org
CC: devicetree@...r.kernel.org
CC: linux-kernel@...r.kernel.org
---
.../microchip/mpfs-beaglev-fire-fabric.dtsi | 82 -------------------
.../boot/dts/microchip/mpfs-beaglev-fire.dts | 5 --
2 files changed, 87 deletions(-)
delete mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
deleted file mode 100644
index e153eaf9b90e..000000000000
--- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-
-/ {
- fabric_clk3: fabric-clk3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- };
-
- fabric_clk1: fabric-clk1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- fabric-bus@...00000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
- <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
- <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
- <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
- <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
-
- cape_gpios_p8: gpio@...00000 {
- compatible = "microchip,coregpio-rtl-v3";
- reg = <0x0 0x41100000 0x0 0x1000>;
- clocks = <&fabric_clk3>;
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <16>;
- gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
- "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
- "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
- "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
- };
-
- cape_gpios_p9: gpio@...00000 {
- compatible = "microchip,coregpio-rtl-v3";
- reg = <0x0 0x41200000 0x0 0x1000>;
- clocks = <&fabric_clk3>;
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <20>;
- gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
- "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
- "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
- "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
- "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
- };
-
- hsi_gpios: gpio@...00000 {
- compatible = "microchip,coregpio-rtl-v3";
- reg = <0x0 0x44000000 0x0 0x1000>;
- clocks = <&fabric_clk3>;
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <20>;
- gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
- "B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
- "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
- "XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
- "XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
- "XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
- "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
- };
- };
-
- refclk_ccc: cccrefclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
-};
-
-&ccc_nw {
- clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
- <&refclk_ccc>, <&refclk_ccc>;
- clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
- "dll0_ref", "dll1_ref";
- status = "okay";
-};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
index 47cf693beb68..aae239d79162 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
@@ -5,7 +5,6 @@
#include <dt-bindings/gpio/gpio.h>
#include "mpfs.dtsi"
-#include "mpfs-beaglev-fire-fabric.dtsi"
/* Clock frequency (in Hz) of MTIMER */
#define MTIMER_FREQ 1000000
@@ -183,10 +182,6 @@ &refclk {
clock-frequency = <125000000>;
};
-&refclk_ccc {
- clock-frequency = <50000000>;
-};
-
&rtc {
status = "okay";
};
--
2.51.0
Powered by blists - more mailing lists