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Message-ID: <CALHNRZ8BKSLi3V6=iubCdde2Hb+84Fj8vzTTcCvmRqA6vS8Z8g@mail.gmail.com>
Date: Tue, 21 Oct 2025 13:29:04 -0500
From: Aaron Kling <webgeek1234@...il.com>
To: webgeek1234@...il.com
Cc: "Rafael J. Wysocki" <rafael@...nel.org>, Viresh Kumar <viresh.kumar@...aro.org>,
Thierry Reding <thierry.reding@...il.com>, Jonathan Hunter <jonathanh@...dia.com>,
linux-pm@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] cpufreq: tegra186: add OPP support and set bandwidth
On Tue, Oct 21, 2025 at 1:28 PM Aaron Kling via B4 Relay
<devnull+webgeek1234.gmail.com@...nel.org> wrote:
>
> From: Aaron Kling <webgeek1234@...il.com>
>
> Add support to use OPP table from DT in Tegra186 cpufreq driver.
> Tegra SoC's receive the frequency lookup table (LUT) from BPMP-FW.
> Cross check the OPP's present in DT against the LUT from BPMP-FW
> and enable only those DT OPP's which are present in LUT also.
>
> The OPP table in DT has CPU Frequency to bandwidth mapping where
> the bandwidth value is per MC channel. DRAM bandwidth depends on the
> number of MC channels which can vary as per the boot configuration.
> This per channel bandwidth from OPP table will be later converted by
> MC driver to final bandwidth value by multiplying with number of
> channels before being handled in the EMC driver.
>
> If OPP table is not present in DT, then use the LUT from BPMP-FW
> directy as the CPU frequency table and not do the DRAM frequency
> scaling which is same as the current behavior.
>
> Signed-off-by: Aaron Kling <webgeek1234@...il.com>
> ---
> drivers/cpufreq/tegra186-cpufreq.c | 152 +++++++++++++++++++++++++++++++++++--
> 1 file changed, 145 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/cpufreq/tegra186-cpufreq.c b/drivers/cpufreq/tegra186-cpufreq.c
> index 136ab102f636aa57741639ed1909d095881c14d3..35f1c1371f6a1688c35f3ba012b9f008fba83d74 100644
> --- a/drivers/cpufreq/tegra186-cpufreq.c
> +++ b/drivers/cpufreq/tegra186-cpufreq.c
> @@ -8,6 +8,7 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/platform_device.h>
> +#include <linux/units.h>
>
> #include <soc/tegra/bpmp.h>
> #include <soc/tegra/bpmp-abi.h>
> @@ -58,7 +59,7 @@ static const struct tegra186_cpufreq_cpu tegra186_cpus[] = {
> };
>
> struct tegra186_cpufreq_cluster {
> - struct cpufreq_frequency_table *table;
> + struct cpufreq_frequency_table *bpmp_lut;
> u32 ref_clk_khz;
> u32 div;
> };
> @@ -66,16 +67,121 @@ struct tegra186_cpufreq_cluster {
> struct tegra186_cpufreq_data {
> void __iomem *regs;
> const struct tegra186_cpufreq_cpu *cpus;
> + bool icc_dram_bw_scaling;
> struct tegra186_cpufreq_cluster clusters[];
> };
>
> +static int tegra_cpufreq_set_bw(struct cpufreq_policy *policy, unsigned long freq_khz)
> +{
> + struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
> + struct device *dev;
> + int ret;
> +
> + dev = get_cpu_device(policy->cpu);
> + if (!dev)
> + return -ENODEV;
> +
> + struct dev_pm_opp *opp __free(put_opp) =
> + dev_pm_opp_find_freq_exact(dev, freq_khz * HZ_PER_KHZ, true);
> + if (IS_ERR(opp))
> + return PTR_ERR(opp);
> +
> + ret = dev_pm_opp_set_opp(dev, opp);
> + if (ret)
> + data->icc_dram_bw_scaling = false;
> +
> + return ret;
> +}
> +
> +static int tegra_cpufreq_init_cpufreq_table(struct cpufreq_policy *policy,
> + struct cpufreq_frequency_table *bpmp_lut,
> + struct cpufreq_frequency_table **opp_table)
> +{
> + struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
> + struct cpufreq_frequency_table *freq_table = NULL;
> + struct cpufreq_frequency_table *pos;
> + struct device *cpu_dev;
> + unsigned long rate;
> + int ret, max_opps;
> + int j = 0;
> +
> + cpu_dev = get_cpu_device(policy->cpu);
> + if (!cpu_dev) {
> + pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu);
> + return -ENODEV;
> + }
> +
> + /* Initialize OPP table mentioned in operating-points-v2 property in DT */
> + ret = dev_pm_opp_of_add_table_indexed(cpu_dev, 0);
> + if (ret) {
> + dev_err(cpu_dev, "Invalid or empty opp table in device tree\n");
> + data->icc_dram_bw_scaling = false;
> + return ret;
> + }
> +
> + max_opps = dev_pm_opp_get_opp_count(cpu_dev);
> + if (max_opps <= 0) {
> + dev_err(cpu_dev, "Failed to add OPPs\n");
> + return max_opps;
> + }
> +
> + /* Disable all opps and cross-validate against LUT later */
> + for (rate = 0; ; rate++) {
> + struct dev_pm_opp *opp __free(put_opp);
> +
> + opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
> + if (IS_ERR(opp))
> + break;
> +
> + dev_pm_opp_disable(cpu_dev, rate);
> + }
> +
> + freq_table = kcalloc((max_opps + 1), sizeof(*freq_table), GFP_KERNEL);
> + if (!freq_table)
> + return -ENOMEM;
> +
> + /*
> + * Cross check the frequencies from BPMP-FW LUT against the OPP's present in DT.
> + * Enable only those DT OPP's which are present in LUT also.
> + */
> + cpufreq_for_each_valid_entry(pos, bpmp_lut) {
> + struct dev_pm_opp *opp __free(put_opp);
> +
> + opp = dev_pm_opp_find_freq_exact(cpu_dev, pos->frequency * HZ_PER_KHZ, false);
> + if (IS_ERR(opp))
> + continue;
> +
> + ret = dev_pm_opp_enable(cpu_dev, pos->frequency * HZ_PER_KHZ);
> + if (ret < 0)
> + return ret;
> +
> + freq_table[j].driver_data = pos->driver_data;
> + freq_table[j].frequency = pos->frequency;
> + j++;
> + }
> +
> + freq_table[j].driver_data = pos->driver_data;
> + freq_table[j].frequency = CPUFREQ_TABLE_END;
> +
> + *opp_table = &freq_table[0];
> +
> + dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
> +
> + /* Prime interconnect data */
> + tegra_cpufreq_set_bw(policy, freq_table[j - 1].frequency);
> +
> + return ret;
> +}
> +
> static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
> {
> struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
> unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id;
> + struct cpufreq_frequency_table *freq_table;
> + struct cpufreq_frequency_table *bpmp_lut;
> u32 cpu;
> + int ret;
>
> - policy->freq_table = data->clusters[cluster].table;
> policy->cpuinfo.transition_latency = 300 * 1000;
> policy->driver_data = NULL;
>
> @@ -85,6 +191,20 @@ static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
> cpumask_set_cpu(cpu, policy->cpus);
> }
>
> + bpmp_lut = data->clusters[cluster].bpmp_lut;
> +
> + if (data->icc_dram_bw_scaling) {
> + ret = tegra_cpufreq_init_cpufreq_table(policy, bpmp_lut, &freq_table);
> + if (!ret) {
> + policy->freq_table = freq_table;
> + return 0;
> + }
> + }
> +
> + data->icc_dram_bw_scaling = false;
> + policy->freq_table = bpmp_lut;
> + pr_info("OPP tables missing from DT, EMC frequency scaling disabled\n");
> +
> return 0;
> }
>
> @@ -102,6 +222,10 @@ static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
> writel(edvd_val, data->regs + edvd_offset);
> }
>
> + if (data->icc_dram_bw_scaling)
> + tegra_cpufreq_set_bw(policy, tbl->frequency);
> +
> +
> return 0;
> }
>
> @@ -134,7 +258,7 @@ static struct cpufreq_driver tegra186_cpufreq_driver = {
> .init = tegra186_cpufreq_init,
> };
>
> -static struct cpufreq_frequency_table *init_vhint_table(
> +static struct cpufreq_frequency_table *tegra_cpufreq_bpmp_read_lut(
> struct platform_device *pdev, struct tegra_bpmp *bpmp,
> struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id,
> int *num_rates)
> @@ -229,6 +353,7 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev)
> {
> struct tegra186_cpufreq_data *data;
> struct tegra_bpmp *bpmp;
> + struct device *cpu_dev;
> unsigned int i = 0, err, edvd_offset;
> int num_rates = 0;
> u32 edvd_val, cpu;
> @@ -254,9 +379,9 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev)
> for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) {
> struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
>
> - cluster->table = init_vhint_table(pdev, bpmp, cluster, i, &num_rates);
> - if (IS_ERR(cluster->table)) {
> - err = PTR_ERR(cluster->table);
> + cluster->bpmp_lut = tegra_cpufreq_bpmp_read_lut(pdev, bpmp, cluster, i, &num_rates);
> + if (IS_ERR(cluster->bpmp_lut)) {
> + err = PTR_ERR(cluster->bpmp_lut);
> goto put_bpmp;
> } else if (!num_rates) {
> err = -EINVAL;
> @@ -265,7 +390,7 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev)
>
> for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) {
> if (data->cpus[cpu].bpmp_cluster_id == i) {
> - edvd_val = cluster->table[num_rates - 1].driver_data;
> + edvd_val = cluster->bpmp_lut[num_rates - 1].driver_data;
> edvd_offset = data->cpus[cpu].edvd_offset;
> writel(edvd_val, data->regs + edvd_offset);
> }
> @@ -274,6 +399,19 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev)
>
> tegra186_cpufreq_driver.driver_data = data;
>
> + /* Check for optional OPPv2 and interconnect paths on CPU0 to enable ICC scaling */
> + cpu_dev = get_cpu_device(0);
> + if (!cpu_dev) {
> + err = -EPROBE_DEFER;
> + goto put_bpmp;
> + }
> +
> + if (dev_pm_opp_of_get_opp_desc_node(cpu_dev)) {
> + err = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
> + if (!err)
> + data->icc_dram_bw_scaling = true;
> + }
> +
> err = cpufreq_register_driver(&tegra186_cpufreq_driver);
>
> put_bpmp:
>
> ---
> base-commit: 211ddde0823f1442e4ad052a2f30f050145ccada
> change-id: 20251021-tegra186-icc-p1-8455e61d453d
>
> Best regards,
> --
> Aaron Kling <webgeek1234@...il.com>
This was originally part of a larger series [0], but it was requested to
be split into smaller series.
Aaron
[0] https://lore.kernel.org/r/20250909-tegra186-icc-v2-0-09413724e781@gmail.com
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